Si基应变多子沟道TFET研究

As MOSFET scaling has attained the nano scale, alternative concepts are intensively being investigated. The Tunnel-FET (TFET) transistor, compatible with CMOS technology but with a different operating principle (tunneling conduction mechanism), appears as a promising solution to replace the conventional MOSFET. Unlike MOSFET, the ON current of TFET is not only limited by the electron transport but also by the electron injection due to band to band tunneling, so TFET presents better short channel effect and a subthreshold swing lower than 60mV/dec, reducing the power dissipation. However, owing to 1.12eV band gap of Si material and minority carriers in the thin inversion layer, the tunneling probability, tunneling area and carrier mobility of Si TFET are low, making the ON current of Si TFET only in the range of 0.1-10μA/μm, much less than the ON current level of MOSFET.To boost the ON current of Si TFET, this project will design a new type of TFET, using the majority carriers of semiconductor as conductive channel. Owing to the much narrower band gap and higher carrier mobility, Si-based strained materials are chosen for the new TFET. Thus, a L-type tunnel line will be easily to obtained, enlarging the tunneling region greatly. The suppressing structure of OFF current will also be studied. With the help of ideas above, the performance of Si-based TFET will be improved greatly. The influence of interface state and traps on I-V, C-V characteristics will be discussed and the model of threshold voltage, ON current, OFF current, etc, will be established. Finally, the preparation of the device samples will be carried out, to indicate the validity of our design. This project can provide valuable foundation for the application of Si-based TFET in nano chips.

纳米时代，MOSFET越来越接近其物理极限，采用新原理、新器件以替代MOSFET成为了必然。基于隧穿原理的TFET具有良好亚阈摆幅和静态功耗，是有效候选器件之一。然而，由于Si TFET隧穿几率低、隧穿面积小、载流子迁移率损失严重，其开态电流远低于MOSFET的开态电流，是制约其发展的关键瓶颈。为解决Si TFET所面临的问题，本项目拟基于Si基应变材料、开展多子沟道TFET基础理论与技术研究。该器件创新的采用多数载流子形成沟道并利用Si基应变材料形成“L”型隧穿面，其载流子迁移率高、隧穿几率与隧穿面积大，可极大提升Si TFET的开态电流。本项目将重点探索Si基应变多子沟道TFET形成机理与工作机制，研究其开关电流比优化方法，建立器件结构模型，分析其阈值电压、开/关态电流、亚阈摆幅等电学特性随关键物理参数的变化规律，开发器件工艺，制备器件样品，为Si基TFET在纳米芯片中的应用奠定基础。

传统Si TFET隧穿几率低、隧穿面积小、载流子迁移率损失严重，其开态电流远低于MOSFET的开态电流，是制约其发展的关键瓶颈。为了克服常规Si TFET所面临的问题，本项目重点研究了以应变Si、SiGe、GeSn、GePb为代表的Si基应变材料制备方法与表征技术，建立了基于Si基应变材料的多子沟道TFET器件模型，并研究了其关键电学特性；探索了多子沟道TFET的优化方法与技术，提出了Si基应变双栅多子沟道TFET、基于PD-SOI的应变多子沟道TFET、L型多子沟道应变TFET等多种开态电流增强的多子沟道器件模型，以及带场板的应变多子沟道器件、台阶状氧化层应变多子沟道器件等关态电流降低的多子沟道器件模型，并研究了上述器件的关键电学特性，探讨了金属功函数、掺杂浓度、器件层厚度等关键参数对其开态电流、关态电流、亚阈值摆幅等电学特性的影响；基于上述成果，研究了多子沟道器件制备工艺，开发了Si基应变多子沟道器件制备流程，制备了Si基应变多子沟道器件，获得了Si基应变多子沟道TFET器件制备方法与技术。研究结果表明：所制备的Si基SiGe、GeSn、GePb等应变材料禁带宽度窄化、载流子迁移率提升，可以极大TFET器件的遂穿几率，满足器件制备需要；所设计的常规Si基应变材料的新型PNN型多子沟道TFET，比起常规PiN型TFET，该类器件隧穿面积大、载流子迁移率高，开态电流获得了极大的提升；所提出的五种基于Si基应变材料的新型多子沟道TFET：Si基应变双栅多子沟道TFET、基于PD-SOI的应变多子沟道TFET、L型多子沟道应变TFET、带场板的应变多子沟道器件、台阶状氧化物应变多子沟道器件，遂穿几率高、遂穿面积大，在极大地提高器件的开态电流的同时，抑制了器件的关态电流。本研究成果为TFET器件在低功耗集成电路中的应用，提供了新的解决思路，并奠定了相关理论及技术基础。