硅沟道纳米DG-TFET器件物理，模拟模型和电路设计技术研究

Silicon-based channel nanosize double-gate tunneling field effect transistor (DG-TFET) may be the promise one between all novel device architectures to extend CMOS integrated circuit into 10nm generation beyond after CMOS age, due to a series of advantages, e.g., the compatible with Moore law and traditional CMOS scaling technology, enhanced short-channel effects, breaking up the CMOS subthreshold slope limit of 60mV/Dec at the room temperature, ultra-low operation voltage and power, and the better temperature stability..However, there has no good solutions so far for some key bottlenecks of the nanosize DG-TFET either from the academic study and the industry advancement implementation, which may hinder this kind of device potential application study in the process and performance optimization, and circuit function simulation and development. For example, first one is lacking of the complete and clear device physics theory on the device operation and the simulation T-CAD tools; second is lacking of circuit simulation SPICE model which become very complicated due to many new physics effects involved in the DG-TFET coming from the heavy doping effect, heterjunction, tunneling mechanism and many engineered technology applications; third is lacking of validity verification on the traditional CMOS design technologies,methods,circuit topologies, and scaling theory. .Aiming at the device structure parameter, channel transport mechanism, simulation tool benchmark and calibration, compact device/circuit model and the DG-TFET based circuit design methodology issue, this project will explore how to develop the nanosize DG-TFET three dimension channel potential based device physics theory and provide full energy band NEGF based simulation tool, build an efficient compact device/circuit SPICE model with the multiple device effect self-consistent integration, and establish nanosize DG-TFET based new circuit design technique, methodology, and scaling guildness. .The project deliverables will help device scientists and circuit designers deeply understand the potential and function of the nanosize DG-TFET application in the ultra low power and voltage integrated circuit, know how to realise the optimised circuit performance from the processing technology improvement and circuit topology designing.

硅沟道纳米DG-TFET因与摩尔定律和按比例缩小CMOS技术兼容，同时具有突破CMOS亚阈极限，增强的短沟效应和较高温度稳定性等优点，对于解决10nm以下集成电路超低功耗和电源电压等系列制约是最可能的后CMOS代器件选择。但该类器件的工艺/性能优化和电路模拟等方面目前还有关键瓶颈待解决：一是还无清晰完整的DG-TFET器件理论和模拟工具；二是诸多物理效应复杂化了电路SPICE模型的建立；三是并不清楚传统CMOS电路设计技术和按比例缩小方法对其是否适用。基于此，本项目将从器件结构、沟道传输、模拟与模型、电路设计等层面展开研究：建立DG-TFET三维沟道势理论和模拟工具;发展自洽集成该器件诸多物理效应的SPICE模型;提出以该器件为单元的电路设计新技术和方法。项目成果将阐明DG-TFET用于超低功耗电路可能性和潜力,有助从基本物理上理解该类器件特性，从工艺技术上优化其结构以实现对应电路功能。

本项目“硅沟道纳米 DG-TFET 器件物理，模拟模型和电路设计技术研究”，以课题小组过去的工作内容和成果为基础，发展了基于非平衡格林函数（NEGF）的量子输运相统一的纳米DG-TFET器件数值模拟工具， 实现了纳米硅沟道 DG-TFET 器件模拟工具和器件/电路 SPICE 模型发展，验证对应的电路功能，发展了纳米DG-TFET电路设计技术和方法，以验证的纳米DG-TFET电路模拟SPICE模型为基础，TEST各种以DG-TFET作为基本结构单元的传统电路功能，比如反相器，环振电路等。在本项目的执行过程中，我们按照研究计划展开了一系列相应的工作。截止至2019年12月项目结束时，我们较为圆满地完成了研究任务，在学术上取得可喜成果，申请发明专利5项， 发表学术论文19 篇， 申请并获得授权软件著作权6项， 培养博士后3人， 研究生3位， 为我国在该方面的学术发展奠定了一定基础，并为以后DG-TFET集成电路产品进行先进工艺发展和电路设计提供一定的理论指导和优化设计技术。另外，项目组还组织举办了包括第8届IWCM (International Workshop of Compact Modeling)等三场国际国内学术会议，邀请了众多与项目相关的纳米器件和模拟及模型方面的专家，对我们项目的开展提供了很宝贵的专业建议。本项目的研究工作进一步增强了我们研究小组在半导体纳米FinFET领域的研究水平，也增强了我们在该领域的国际影响力。