SOI基高迁移率双沟道材料制备研究

As strained Si (sSi) technology is able to improve the CMOS' performance by introducing stress into the conventional Si device to enhance the carrier mobility, strained Si technology is considered as one of the core technologies to support the development of IC industry along the Moore's law. However, compared to the electron mobility, the enhancement of the hole mobility in strained Si is limited and relatively insufficient. In this project, the researchers propose to fabricate a SOI structure with sSi-SiGe dual-channel material in which strained Si could provide high electron mobility, and SiGe could provide comparable hole mobility simultaneously. Therefore, NMOS with high electron mobility and PMOS with high hole mobility can be realized on one single substrate as proposed. .The ultimate aim of this project is to achieve 6 inch SOI wafer with sSi-SiGe dual-channel material, and provide high-end substrates for future electronic devices in micro/nanoelectronic era as the process technology is approaching the 22nm logic node. The project will focus on the following three aspects to carry out scientific researches:.(1).Systematically investigating the physical mechanism underlying dislocations evolution and stress relaxation during Si/SiGe heterostructure epitaxial growth and oxidation-condensation process..(2).Extensively investigating the influence of physical properties of strained materials on carrier mobility; .(3).Optimizing the process parameters for sSi-SiGe-OI fabrication, and exploring the proper electronic devices based on sSi-SiGe dual-channel material..SOI基高迁移率双沟道材料制备研究.dual-channel high mobility SOI material research

应变硅技术通过在传统的体硅器件中引入应力增加载流子迁移率，从而提高CMOS 器件的性能，因而被认为是推动集成电路沿摩尔定律继续发展的核心技术之一。本项目针对应变硅空穴迁移率相对较低这一问题，提出将应变硅与空穴迁移率高的SiGe材料相结合，形成绝缘体上sSi-SiGe（sSi-SiGe-OI） 双沟道高迁移率新材料，可以用来在同一衬底上实现高电子迁移率的NMOS 以及高空穴迁移率的PMOS。.本项目目标研制成功6英寸sSi-SiGe-OI双沟道高迁移率晶圆片，深入研究Si/SiGe材料异质外延与氧化浓缩过程中缺陷演变以及应变维持与释放等得物理机制与规律，并探索双应变沟道材料在器件制备过程中的行为，研究应变材料特性对载流子迁移率的影响，优化材料关键参数，为特征线宽22 nm节点以下微纳电子时代提供高端硅基衬底材料。

应变硅技术通过在传统的体硅器件中引入应力增加载流子迁移率，从而提高CMOS 器件的性能，因而被认为是推动集成电路沿摩尔定律继续发展的核心技术之一。本项目针对应变硅空穴迁移率相对较低这一问题，利用外延技术、离子注入技术、键合与分离等薄膜转移技术，将应变硅与空穴迁移率高的SiGe材料相结合，制备出绝缘体上sSi-SiGe（sSi-SiGe-OI） 双沟道高迁移率新材料，在同一个衬底上实现高电子迁移率的NMOS 以及高空穴迁移率的PMOS。揭示了异质薄膜制备、退火行为、界面特性等物理机制，研制成功6英寸sSi-SiGe-OI双沟道高迁移率晶圆片，为特征线宽22 nm节点以下微纳电子时代提供新型SOI基衬底材料。