One of the most potential approaches to enhance the structural reliability of electronics in defense industry is encapsulating the electronics in polymer materials, a process called "potting". It provides many benefits such as long durability, enhanced resistance to moisture, erosion, as well as attenuation of shock loads. However, the main issue with potting treatment is that it usually exacerbates thermal stress in electronics since potting material has poor thermal conductivity. It is therefore the objective of this project to seek possible ways to mitigate the detrimental influence of thermal stress on the potted PCB assembly. In this project, we will use both theoretical and experimental methods to determine the distribution of thermal stress for the potted configuration, and to explore the mechanisms underlying the failure of the interconnection due to thermal stress, in order to guide the design of potted electronics. Particularly, we intend to cover the following topics: (i) Analytical or semi-analytical solution of thermal stress in the potted configuration composed of PCB, IC package and polymer potting material; (ii) Numerial and experimental study of the thermal stress distribution and its dependence on various parameters such as potting properties, configuration geometry, loading condition and boundary conditions; (iii) Crack initiation and propagation on the interface in the interconnection between the PCB and IC package, especially for the potted case; (iv) Investigation of the size effect in the thermal stress distribution and failure of interconnection for microelectronics, especially under the framework of strain gradient or nonlocal elasticity theorem; (v) Developing the homogenization method for modeling the interconnection, considering plasticity of solders and viscoelasticity of underfill materials. This project aims at increasing the reliability of electronics under extreme working conditions such as gun launch process, and is of significant importance to national defense industry.
聚合物充填是将电路板整体封装于聚合物材料中以提高设备可靠性的新方法,它在国防工业中有很大应用潜力。热应力引起的失效是该方法应用中急需解决的问题。本项目通过研究充填对电路板中的热应力的影响,探讨接合薄弱处在热载荷作用下的失效机理,来优化电路板及其充填设计,从而为减小热应力影响,提高电子设备的结构可靠性提供依据。研究内容包括:寻求充填构型下电路板中热应力场的解析或半解析解;结合模拟和实验,研究聚合物材料性能、几何构型、加载方式和边界条件等参数对电路板中热应力分布的影响;研究界面裂纹的诱发和扩展,探究接合层的失效机理并考察其尺度效应;将接合层均一化为各向异性材料模型,并考虑焊点塑性和底部填充物的粘弹性来改进这一模型。本研究对推广聚合物充填方法来提高电子设备在极端工况下的可靠性,进而对国防安全具有重要意义。
聚合物整体充填法可以显著提高电子设备的服役和储存可靠性,在国防工业中有较强应用潜力,但该方法通常加剧了结构中热应力,容易引起电路板失效。本项目针对这一技术现状,研究了聚合物充填电路板在热力载荷下的失效问题,旨在为减小热应力影响,提高聚合物充填方法可靠性提供理论储备。研究内容包括:通过解析求解得到充填构型应力场的理论解;通过有限元模拟研究充填电路板在各种工况下的电子器件和接合层中的热应力分布;通过分子动力学方法模拟研究聚合物填充物的力学行为;进行实验验证。本项目取得的研究成果有(1)基于细观力学理论发展了电子器件接合层材料均一化的方法,极大提高了计算效率;(2)确定了各个几何和材料参数对器件和接合层热应力的影响;(3)指出了现有分子动力学方法在模拟固体变形时存在能量不守恒现象,提出了合理的变形模拟方案;本项目的研究可以为进一步优化电路板的聚合物充填设计提供理论指引,克服和减小热应力引起的失效,对推广聚合物充填方法的应用具有较强意义。
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数据更新时间:2023-05-31
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