硅锗锡/锗锡异质结隧穿场效应晶体管亚阈值摆幅退化机制研究

The aim of this project is to explore and control the physical mechanism of subthreshold swing degradation of SiGeSn/GeSn hetero tunneling field effect transistor. This topic is focused on the key issues in the energy band model of SiGeSn/GeSn hetero junction and the physical mechanism of subthreshold swing degradation due to traps in hetero-tunneling junction and interface states in channel region. In experiment, this topic is to explore the critical technical issues in the growth of source materials and surface passivation during the fabrication process of high-performance SiGeSn/GeSn hetero junction device, and to realize hetero junction TFET with abrupt subthreshold swing and high tunneling current in the end. Firstly, the impact of the density and location of the traps in tunneling junction, the density and energy distribution of interface states in channel on subthreshold swing and tunneling current will be analyzed theoretically. The energy band model of SiGeSn/GeSn and the electrical properties compactness model of TFET device will be built consequently. Secondly, the influence of the material quality of tunneling junction and the processing of surface passivation on key electrical properties will be analyzed experimentally. Finally, we will compare the experimental results and theoretical modeling results and correct the physical model accordingly. The project will lay a theoretical and experimental foundation for fabrication of high efficiency SiGeSn/GeSn tunneling junction, and further realization of high performance GeSn hetero junction TFET.

本项目以探索并控制SiGeSn/GeSn异质结隧穿场效应晶体管（TFET）器件亚阈值摆幅退化机制为目标，围绕隧穿结陷阱、沟道界面态导致器件亚阈值摆幅退化机制和SiGeSn/GeSn异质结能带计算模型等关键科学问题。探索高性能SiGeSn/GeSn异质结器件实现过程中的源极材料生长和表面钝化等关键技术问题，实现陡峭亚阈值摆幅、高隧穿电流异质结TFET。首先，理论研究隧穿结陷阱密度和空间位置、沟道界面态密度和能量分布对器件亚阈值摆幅和隧穿电流的影响机制，进而建立SiGeSn/GeSn能带计算和TFET器件电学性能模拟紧凑模型；其次，实验探索隧穿结材料质量和表面钝化工艺等因素对器件亚阈值摆幅等关键电学性能的影响；最后，通过实验测试与理论模拟结果的对比，对相关物理模型进行校正。本课题将为高效SiGeSn/GeSn隧穿结的制备以及进一步研制GeSn异质结TFET奠定理论和实验基础。

本项目以探索并控制SiGeSn/GeSn异质结隧穿场效应晶体管（TFET）器件亚阈值摆幅退化机制为目标，围绕隧穿结陷阱、沟道界面态导致器件亚阈值摆幅退化机制和SiGeSn/GeSn异质结能带计算模型等关键科学问题。探索高性能SiGeSn/GeSn异质结器件实现过程中的源极材料生长和表面钝化等关键技术问题，实现陡峭亚阈值摆幅、高隧穿电流异质结TFET。首先，理论研究隧穿结陷阱密度和空间位置、沟道界面态密度和能量分布对器件亚阈值摆幅和隧穿电流的影响机制，进而建立SiGeSn/GeSn能带计算和TFET器件电学性能模拟紧凑模型；其次，实验探索隧穿结材料质量和表面钝化工艺等因素对器件亚阈值摆幅等关键电学性能的影响；最后，通过实验测试与理论模结果的对比，对相关物理模型进行校正。本课题将为高效SiGeSn/GeSn隧穿结的制备以及进一步研制GeSn异质结TFET奠定理论和实验基础。