针对InGaAs围栅纳米线隧穿场效应晶体管亚阈值摆幅退化的机理研究、模型改进及结构优化

Tunneling field effect transistor (TFET) has been regarded as one of the most promising ultra low power devices for its theoretical subthreshold swing (less than 60 mV/dec). However, trap-assisted tunneling leads to subthreshold swing degradation, which extremely limit application and development of TFET. In this project, first-principle calculation, analytical modeling, TCAD simulation and technology experiment will be employed to solving the degradation problem of InGaAs surrounding-gate nanowire TFET. First, the formation mechanism of the trap at the gate dielectric/semiconductor interface and heterojunction interface is studied. Then the relationship between trap's parameter (such as structure, energy level and position) and trap assisted tunneling is investigated. Based on that, the physical mechanism of subthreshold swing degradation will be determined. With considering the influences of quantum confinement and trap-assisted tunneling, two-dimensional analytical model will be established. Optimization structure will be presented by analyzing the effect of gate channel underlap and gate source overlap on electrical performance of the device. In order to experimentally demonstrate the validity of proposed degradation mechanism, analytical model and optimized structure, InGaAs planar single-gate TFET will be fabricated based on planar bulk technology. This project will provide not only physical insight, but also flexible process choices for optimizing the performance of InGaAs surrounding-gate nanowire TFET.

隧穿场效应晶体管（TFET）理论上具有小于60 mV/dec的亚阈值摆幅，在超低功耗领域的应用潜力巨大。然而，界面陷阱引起的陷阱辅助隧穿导致TFET亚阈值摆幅严重退化，极大地限制了TFET的应用与发展。为从根本上解决亚阈值摆幅退化问题，拟针对InGaAs围栅纳米线TFET，采用第一性原理计算、理论建模、TCAD模拟以及工艺实验相结合的方法，分析栅介质/半导体界面以及异质结界面处陷阱的形成机理，确定陷阱结构、能级、位置与陷阱辅助隧穿之间的关系，明确亚阈值摆幅退化机理；考虑陷阱辅助隧穿与量子限制效应的影响，建立二维解析模型；研究栅沟不覆盖结构和栅源覆盖结构对器件电学特性的影响，提出可抑制亚阈值摆幅退化的新结构；通过实验制备InGaAs平面单栅TFET及相应优化结构，间接验证上述所提退化机理、解析模型以及优化结构。本研究将为制备高性能InGaAs围栅纳米线TFET器件奠定理论基础并提供工艺指导。

隧穿场效应晶体管（TFET）理论上具有小于60 mV/decade的亚阈值摆幅，在超低功耗领域的应用潜力巨大。然而，开启电流小、双极效应严重以及界面陷阱引起的亚阈值摆幅退化等问题极大地限制了TFET器件的应用与发展。为从根本上解决亚阈值摆幅退化问题，有效改善TFET器件的开启特性并抑制其双极效应，本项目针对多种类型TFET器件，采用理论分析、数学建模与TCAD仿真相结合的方法开展相关研究。首先，分析了栅介质/半导体界面以及异质结界面处陷阱的形成机理，确定了陷阱结构、能级、位置与陷阱辅助隧穿之间的关系，明确了亚阈值摆幅退化机理，建立了陷阱辅助隧穿理论模型以及TFET器件电流模型，为后续开展TFET器件结构优化与改进奠定理论基础；接着，重点研究了栅沟不覆盖结构、栅源覆盖结构以及绝缘隔离侧墙结构对器件电学特性的影响，提出了全新的L型InGaAs异质结TFET新结构。结果表明，与传统TFET结构相比，L型InGaAs异质结TFET器件不仅可以显著提升TFET的开启电流，还可以有效抑制双极效应，极大改善了TFET器件的射频/模拟特性；最后，为彻底解决陷阱辅助隧穿的影响并克服源漏超陡掺杂带来的工艺困难，基于电荷等离子体概念，提出了全新的L型栅电荷等离子体TFET结构。该结构在不掺杂的衬底上利用金属与半导体的功函数差实现源漏区的“反型”，从根本上解决了陷阱辅助隧穿引起的亚阈值摆幅退化的问题。此外，与传统TFET器件相比，L型电荷等离子体TFET器件通过改变感应源漏与栅的相对位置，有效解决了栅源金属间隔的问题，有效提升了TFET器件的开启电流。另外，由于源漏金属不在统一工艺平面内，栅电极对源漏产生不对称的影响，因此器件的双极效应也得到了有效抑制。综上，本项目的研究成果为今后制备高性能TFET器件并实现超低功耗集成电路设计设计奠定了坚实的基础。