高介电栅极有机薄膜晶体管的湿法制备及界面物理研究

In recent years, organic thin film transistors(OTFTs) have been made large progress from material design and device design. In our country, high-mobility organic semiconductors have reached the international level. However, fabrication of high-performance and low-voltage OTFTs have the large challenges in materials and technologies. In this proposal, we will use high-k relaxor ferroelectric polymer (k, 60) as the gate insulator and latest high-mobility organic semiconductors to fabricate high-performance and low-voltage OTFTs by solution processing. Because the high-k dielectric has strong dipoles, we will use high-k dielectric to study interaction of semiconductors and dielectrics and the charge-transport in the interface of semiconductors and dielectrics. Moreover, high-k dielectrics can induce high carrier density under the low voltage. We will observe the electrical properties of OTFTs under the extreme high carrier density. We will find out the inner physical mechanism of semiconductor-dielectric interaction and the charge-transporting mechanism in the interfaces of semiconductors and dielectrics through high-k dielectric. It will provide the theoretical foundation for applications of high-k materials in OTFTs. On the other hand, we will also explore the novel and universal approaches of interface modifications for better charge-transporting interface and better performances of low-voltage OTFTs.

近年来，有机薄膜晶体管(OTFT)从材料到器件设计都取得了巨大的进步。国内在高迁移率有机半导体研究方面已经达到国际水平，但制备低压高性能的OTFT在材料与技术上都有极大的挑战。本项目将利用高介电常数（k）有机弛豫铁电材料P(VDF-TrFE-CFE)(k 约60)作为栅极介电层，与最新高迁移率有机半导体结合，用溶液法实现高性能低压OTFT的制备。利用高k电介质有极性强的电偶极子，研究电介质与半导体接触的相互作用及对电荷传输的影响。同时，高k电介质也可以在较低的电场下诱导高的载流子浓度，观察在极高的载流子浓度下OTFT的电学性能。通过高k材料，弄清半导体与电介质相互作用的内在物理机理以及电荷在界面的传输机制，为发展与优化高k 材料在OTFT中的应用提供理论基础。另外，为了得到合适的电荷传输界面，将发展新型、普适性的界面修饰方法，提高电荷在界面的传输性能，制备出更高性能的低压OTFT。

有机薄膜晶体管高的操作电压是其在应用中的巨大挑战。高k电介质的使用可以有效降低操作电压。然而，目前有机晶体管中能使用电介质材料比较少，介电系数普遍比较低。另一方面，高k电介质在实际使用中可能与半导体存在兼容性问题，导致器件性能降低。本项目通过研究有机薄膜晶体管face-on、edge-on两类薄膜结构的半导体薄膜与高k栅极电介质之间相互作用，发现face-on薄膜与高k电介质之间存在强的Fröhlich极化子作用，导致器件迁移率等电学性能下降。探索出通过低k电介质修饰半导体与高k电介质之间的界面，可以抑制这种作用，提高器件的电学性能。发现Cytop，PVA和PMMA都可以作为好的P(VDF-trFE-CTE)修饰材料，特别是发现可溶性PMMA也可以很好修饰P(VDF-trFE-CTE)与半导体之间相互作用。用P(VDF-trFE-CTE)作为栅极，ZnO作为半导体活性层，通过界面修饰制备了操作电压3V，迁移率达13.6 cm2/Vs，开关比高于10^5的低压晶体管。采用C8BTBT为活性材料，制备出操作电压5V，迁移率达超过3 cm2/Vs，开关比高于10^5的低压晶体管。我们的研究为高k介电材料在柔性电子器件应用提供理论和实践上的指导。