应用于未来CMOS器件中的叠层纳米线和亚纳米高介电系数介质膜的制备技术的开发

Metal-Oxide-Semiconductor (MOS) based microelectronic technology, being the most important driving force for the development of almost all kinds of modern technologies over the last five decades, will continue to lead the technology revolution for at least another couple of decades. The size of MOS devices will be scaled down to less than a decananometer and it structure as well as the fabrication technology will be completely different to the present ones. This project aims at the investitgation of two key technological options - the silicon-on-nothing (SON) stacked nanowires and subnanometer thick gate dielectrics - to be used in the ultimate MOS technology. This work will focus on exploring the optimal processes for the SON stacked nanowire MOS transistor fabrication. We shall conduct a systematic device and process characterization and develop some theoretical models to explain and to predict the performances of the transistors. The availability of high-quality subnanometer-thick high-k gate dielectric film is another key issue for achieving high device performance and viable mass production technology for this kind of transistor. In this work, we shall investigate both the physical structures and the electrical properties of some complex oxides and stacked structures based on the rare earth lanthanum oxide. The material properties associated with electronic structures such as thermal stability, oxygen vacancies, and band structures will be deeply explored. Material interactions between the high-k/silicon substrate, and high-k/metal electrode interfaces are the major origins of device instabilities. We shall examine the interfacial bonding structure, the bonding strain and relaxation, chemical reactions and atomic diffusion at the interfaces.

以金属-氧化物-半导体（MOS）技术为基础的微电子技术，将在未来的二十年间，继续引导着科技革命。而MOS器件的尺寸，将会缩小到十纳米以下。它还将以全新的面貌出现。本研究课题针对终极纳米MOS器件制造的两个关键工艺――悬空硅纳米线和亚纳米high－ｋ栅介质膜的制造――做出全面深入的研究。 我们将为多通道硅纳米线 MOS管的制造技术提供材料和工艺优化方案。我们将深入研究这种晶体管的载流子传输机制，器件特性，以及可靠性问题并开发出相关的精简模型。基于高介电常数(ｈｉｇｈ－k)的栅极电介质的使用可以有效地提升现有MOS器件的技术指标，high-k介质膜将是未来纳米尺度MOS器件的必然选择。然而，为了将这种新材料纳入到现有的MOS技术中，有很多问题需要解决。在本研究中，我们会探寻一些基于稀土金属镧的复合氧化物及其叠层结构的高性能亚纳米栅介质膜，从而进一步提高MOS器件的电学特性和稳定性。

本研究课题针对终极纳米MOS器件制造的两个关键工艺: (a)悬空硅纳米线和(b)亚纳米high-k栅介质膜的制造,做了全面深入的研究。 我们为多通道硅纳米线 MOS管的制造技术提供了材料和工艺的优化方案，并对这种晶体管的载流子传输机制、器件特性，以及可靠性问题做了深入研究，开发出相关的精简模型。基于高介电常数(high-k)的栅极电介质的使用有效地提升了现有MOS器件的技术指标，high-k介质膜将是未来纳米尺度MOS器件的必然选择。然而，要将这种新材料纳入到现有的MOS技术中，还有很多问题需要解决。在本研究中，我们开发了多种高介电常数材料的制备工艺与电学特性，包括氧化铪，氧化镧，基于稀土金属镧的复合氧化物，氧化铈，氧化钽，及其叠层结构的高性能亚纳米栅介质膜，从而进一步提高MOS器件的电学特性及其稳定性。