针对数字集成电路中软错误与老化的协同防护

Along with integrated circuit technology scaling, soft errors caused by high energy particles in aerospace application environment seriously threaten the stability of the circuit. Meanwhile, technological progress accelerates circuit performance degradation caused by circuit aging. Collaborative protecting integrated circuits from both soft errors and aging is in demand in deep space exploration application fields, which is paid little attention to in existing research works. This project focuses on the problem of digital integrated circuits soft errors and aging collaborative protection at circuit level and studies 1) the gate input reordering strategy based collaborative protection method with no additional gate area overhead, which exploits the stack effect of transistors to exchange gate inputs, reducing the soft error susceptibility and aging degree. 2) the gate resizing strategy based collaborative protection method, which enlarge the gate size to increase gate node critical charge, raising the immunity of circuit against soft errors and providing circuit with more timing margin to mitigate aging. 3) the dynamic voltage adjustment strategy based collaborative protection method, which increases gate node critical charge by increasing supply voltage, reducing the soft error rate of circuit while compensating circuit performance loss due to aging. It is used in different circuit blocks in order to protect circuit from both soft errors and aging. The research of this project has important theoretical and practical significance to improve the reliability of digital integrated circuit and extend the life of the circuit.

伴随集成电路工艺尺寸不断减小，航空航天应用环境中高能粒子引发的软错误对电路稳定性的威胁更加严重，同时工艺进步导致老化引起的电路性能衰退加速。现有研究很少关注对于软错误与老化的协同防护，而这在深空探索领域很有必要。本项目开展针对数字集成电路中软错误与老化的电路级协同防护研究，主要包括：1)基于门输入信号交换的协同防护方法。利用晶体管的堆叠效应，通过交换门输入信号降低软错误易感性和老化程度，是一种无门面积开销的方案。2) 基于门尺寸调整的协同防护方法。通过增加门尺寸，提高节点临界电荷，提升电路的软错误免疫力，并提供足够时序余量，延缓电路老化。3) 基于动态电压调整的协同防护方法。通过提升工作电压来提高节点临界电荷，降低软错误率，同时补偿电路由于老化造成的性能损失，在电路不同区域使用该方法，实现对软错误和老化的协同防护。本项目研究将提高数字集成电路可靠性，延长电路寿命，具有重要的理论与实际意义。

随着集成电路工艺尺寸的缩减，老化和软错误带来的可靠性问题越来越显著。课题组针对二者提出了相应的解决方法：a) 对于集成电路老化的检测，提出了可编程的老化感知触发器、容软错误的可编程老化预测传感器和抗老化消除浮空点并自锁存的老化预测传感器，它们能够有效的提前或者电路老化程度，传感器本身的功耗开销和面积开销较以往的传感器取得显著进步；b)对于电路本身结构的老化，插入传输门在电路降低休眠阶段尽可能的最大化老化恢复，从而降低电路老化，还对多输入向量缓解老化的方法提出了针对关键路径和改进遗传算法的占空比求解方式，有效的延缓了电路老化；c)针对集成电路容忍软错误，提出了反馈冗余的容忍SEU和SET锁存器电路结构，有效的提高了软错误容忍结构的延迟、面积开销；d)针对专用集成电路抗老化，提出了延缓p型多米诺电路以及门控电源老化、延长其寿命的手段。本项目研究将延缓电路老化，提高软错误容忍能力，提升集成电路可靠性，具有一定的理论与实际意义。