基于完全自定时技术的可重构高速逐次逼近ADC研究

With the development of advanced CMOS process and innovative design techniques, SAR ADC has been extensively investigated in the field of wideband communication system for its high energy efficiency, and easy reconfiguration. This project intends to work on asynchronous control mechanism, and propose a new fully self-timed technique which can implement both sub-DAC self-timing and comparator self-timing. A new architecture of digital assisted SAR ADC would be proposed, by combining the fully self-timed technique and digital redundancy/compensation technique to co-optimize the parameters of sub-DAC settle error and digital redundancy. Meanwhile, for the consideration of power requirement of reconfigurable ADC, the project would like to design a fully self-timed technique based feedback control circuit, which can adjust static power adaptively in response to the reconfiguration of sampling frequency and resolution. Finally, a 8~12bit, 20MSPS~160MSPS reconfigurable SAR ADC would be design and fabricated. In the whole range of sampling frequency and resolution, figure of merit (FoM) would stay stable.

随着晶体管特征尺寸的缩小以及创造性设计技术的提出，逐次逼近ADC以其高能效，易于重构的特点，开始在宽带通信领域显示出广阔的应用前景。本课题从逐次逼近ADC的异步控制机制入手，探索能同时实现sub-DAC建立自定时以及比较器判决自定时的完全自定时技术，并提出高效高精度的自定时检测机制以及低复杂度实现电路。在此基础上，通过结合数字冗余与校准技术，进行sub-DAC未完全建立误差与冗余度联合优化的研究，实现数字辅助的高速逐次逼近ADC架构。同时，为满足可重构应用的要求，首次提出了一种基于完全自定时技术的静态功耗自适应闭环调节机制。最后，本课题将实现一款8~12Bit分辨率，20MSPS~160MSPS采样率可重构的逐次逼近ADC，在整个重构范围内，能效值FoM始终保持稳定。

模数转换器（ADC）作为连接模拟与数字的桥梁，是当代无线数字通信系统接收机前端的关键模块。随着微电子工艺技术以及电路高速设计技术的发展，传统低速的逐次逼近型模数转换器（SAR ADC）开始向宽带通信应用领域扩展，并逐渐显示出广阔的前景。此外，由于SAR ADC结构简单，其固有的低功耗，高能效的特点在深亚微米工艺条件下显得更加突出。.异步自定时技术是提高SAR ADC转换速度的重要手段，针对传统自定时技术仅实现比较器判决过程自定时的缺点，提出一种利用充放电匹配网络实现sub-DAC建立过程自定时的方法。针对该自定时方法可能引入的建立误差，提出结合冗余技术来校正；提出了一种新型开关电容阵列的翻转机制，极大地降低了其动态翻转功耗；针对多标准多模通信接收机对可重构ADC的需求，基于完全自定时技术，提出一种可根据采样频率自适应调整驱动强度的参考电压缓冲电路；设计了高速低功耗SAR ADC芯片，系统验证表明其性能满足特定宽带无线通信系统的实际需求。.本课题的开展有利于SAR ADC高速、低功耗设计技术的进一步发展，通过拓展与提升SAR ADC的功能与性能，最终有力地推动SAR ADC在宽带通信领域的广泛应用。