基于二级内插的小二进制高速逐次逼近ADC的研究

Analog-to-digital converters (ADCs) are widely used in mixed-signal systems. The developing trend of IEEE 802.11 standards becomes wider bandwidth and higher modulation resolution. For instance, the bandwidth requirement of 802.11ac is 80MHz~160MHz with modulation accuracy of 256-QAM. Additionally, the demand of power consumption keeps decreasing. To satisfy the above requirements, this project is to design a 10-bit ADC with 300-500MS/s and power consumption at level of mW. The 2b/cycle SAR ADC architecture is planned to be utilized to increase the sampling speed. To guarantee the resolution under such a high sampling speed, a 2b/cycle based non-binary approximation technique will be proposed. Also, the error tolerated capability will be significantly improved. Moreover, to reduce the silicon area of ADC, the two-stage interpolation architecture will be proposed, which only needs lower resolution for capacitive DAC array. To demonstrate the proposed techniques, the ADC will be fabricated in 65nm CMOS technology, followed by packaging, testing. Finally, it will be made as an IP core.

模数转换器（ADC）广泛应用于混合信号系统中。IEEE 802.11ac的信号带宽要求为80MHz~160MHz，调制精度为256-QAM，低功耗应用。传统的流水线型ADC，以及时钟交错ADC均需要较大的功耗和芯片面积来实现高速高精度的模数转换，且带有复杂的校准单元。为了满足低功耗，低成本模数转换需求，本项目拟设计以及研究一款采样率300-500MS/s，分辨率10比特，功耗为毫瓦级的高速高精度ADC芯片。该ADC拟采用2比特/采样周期的逐次逼近（SAR）ADC架构。为保证采样高速采样下的精度，本项目拟研究一种针对2比特/采样周期的小二进制逼近方法，以提高逐次逼近过程中的容错能力。此外，为减小芯片面积，本项目拟采用二级内插（预放大器和比较器内插）结构来减小数模转换（DAC）电容阵列。本项目拟采用CMOS 65nm工艺流片，封装，测试以及IP化，对高速高精度的ADC的设计研究提供方法指导。

传统的流水线型ADC，以及时钟交错ADC均需要较大的功耗和芯片面积来实现高速高精度的模数转换，且带有较复杂的校准单元。为了满足低功耗，低成本模数转换需求，本项目设计以及研究一款采样率为300-500MS/s, 分辨率为10比特，功耗为毫瓦级的高速高精度ADC芯片。该ADC拟采用2比特/采样周期的逐次逼近（SAR）ADC架构。为了保证采样高速采样下的分辨率，本项目拟研究一种针对2比特/采样周期的小二进制逼近方法，以提高逐次逼近过程中的容错能力。此外，为了减小芯片面积，本项目拟采用二级内插（预放大器和比较器内插）的结构来减小数模转换（DAC）电容阵列的尺寸。本项目采用了CMOS 40nm工艺流片、封装、测试。本项目完成了预定的研究目标与内容，包括发表IEEE期刊论文2篇等成果。