亚20纳米碳纳米管CMOS器件研究

Owing to its unique structure and excellent electrical properties, especially including ultra-thin body and symmetric band structure between conduct band and valance band, carbon nanotube has been considered as a promising material to build ultra-small CMOS devices. Compared with conventional transistor, carbon nanotube based transistor presents better scaling down behavior, and then can satisfy the requirement of integrated circuits at sub-8 nm technological node. However carbon nanotube CMOS devices with gate length smaller than 100 nm have never been realized experimental. This project aims to explore fabricating the sub-20 nm carbon nanotube CMOS field-effected-transistors with top gate, measuring and investigating their electrical performance, and provide a scheme to optimizing the device performance. Moreover we should estimate the possibility of substituting the mainstreaming silicon CMOS technology through carbon nanotube based technology. In detailed, the research works should focus on three aspects as follows, (1) fabricating carbon nanotube top-gated CMOS devices with gate length smaller than 20nm, and building some simple integrated circuits; (2) Investigating the dependences between device performance and some key structural/technological parameters, providing a scheme to optimizing the performance of sub-20 nm carbon nanotube CMOS devices, and then exploring the scaling limit of gate length and the device performance; (3) Studying the dependences between device performance and contact length of electrode, exploring the scaling limit of contact length, and then further optimizing size of the carbon nanotube CMOS devices.

碳纳米管具有独特的结构和优异的电学性质，特别是超细的管径、导带与价带几乎完全对称的能带结构，因此在构建小尺寸CMOS器件方面极具潜力。碳纳米管晶体管具有更好的尺寸缩减性能，能够满足8纳米以下技术节点的集成电路技术的要求。但是栅长小于100纳米的碳纳米管CMOS顶栅器件尚未实现。本项目探索亚20纳米的碳纳米管顶栅CMOS场效应晶体管器件的制备，测试和研究器件电学特性，并确定优化方案。在此基础上评估碳纳米管集成电路取代硅基CMOS技术的可能性。具体研究目标：（1）制备出栅长小于20纳米的碳纳米管顶栅CMOS器件和简单的集成电路电路；（2）研究主要结构参数和工艺参数对器件的主要性能的影响，给出亚20纳米碳纳米管CMOS器件性能的优化方针，探索碳纳米管器件的栅长缩减极限和性能极限；（3）研究接触电极尺寸缩减对碳纳米管器件性能的影响，探索接触电极尺寸缩减的极限，进而优化碳纳米管CMOS器件面积.

项目主要围绕碳基纳米电子学开展研究，探索碳基电子器件的潜力和优势，推动碳基集成电路技术的发展。项目在碳纳米管器件和集成电路上取得了一系列国际领先的成果，超额完成了研究目标。主要研究成果包括：(a)首次实现了10纳米栅长碳纳米管CMOS器件和5纳米栅长碳纳米管p型器件，器件的本征门延时为50fs，接近了由测不准原理决定的量子极限。(b)在绝缘基底上实现基于碳纳米管 CMOS 器件构建的各种逻辑门电路、编码和译码电路、时序电路、8 管算术逻辑函数发生器单元以及8 位总线电路，以及4位全加法器电路，发展了碳纳米管中等规模集成电路制备方法。碳基集成电路的单级门延时为18 ps, 电路工作频率超过5 GHz。（c）基于平行阵列碳纳米管，实现高性能倍频器和混频器电路，工作频率超过40 GHz。（d） 培养博士研究生 5 人，硕士研究生3人。.项目已发表SCI论文17篇，包括Science 1篇，Nano Lett. 1篇，ACS nano 2篇，Adv. Mater. 1篇。国际国内会议邀请报告7个，申请专利7项，其中有3项已获授权（包括一项美国专利）。发表专著一本。.项目负责人于2014年晋升为北京大学教授，获得了2016年国家自然科学二等奖（排名第二），2016年北京市茅以升青年科技奖，并成为国家重点研发计划（纳米科技）课题“高性能碳基纳米晶体管的制备及大规模集成”负责人。