抗硼扩散高可靠超薄栅介质的制备和特性研究

As the channel length of MOS transistors is reduced to 0.1μm, the thickness of gate oxide needs to be decreased to suppress short channel effect and enhance the current driving capability. Surface-channel PMOSFETs have been used recently to improve short channel effect. But boron in the p-type gate electrode can easily penetrate into the channel region of silicon substrate through the gate oxide during thermal activation, which makes characteristics of transistor unstable. In order to solve these problems, it is important to fabricate highly reliable ultra-thin gate dielectrics with resistance to boron penetration. And an increasing amount of attention has been devoted to it in recent years.In this project research dealing with ultra-thin gate dielectrics was systemically carried out based on the background mentioned above. In addition, nano-scale CMOS device with the channel length of 85nm and good performance has been fabricated. Radiation hardened CMOS/SOI device and circuit, which are promising for military application, were developed based on some research results. The main research content of this project involves in fabrication and characterization of ultra-thin gate oxide, the analysis of related physical mechanism, extraction of ultra-thin gate oxide thickness, the effects of radiation on the electrical characteristics of ultra-thin gate oxide, application of ultra-thin oxide in sub-100nm CMOS devices, development of robust CMOS/SOI device and circuit with improved radiation hardness. Several approaches have been adopted to fabricate ultra-thin gate oxides in our experiments, which included nitrogen-diluted oxidation, gate oxidation on nitrogen-implanted silicon substrate, nitrogen implantation into poly-Si gate electrode and annealing in N2O ambient after gate oxidation. Optimizations of each process were involved at the same time.1. 3-6nm SiO2 gate oxides were prepared by nitrogen-diluted oxidation, in which SPM (H2SO4/H2O2) cleaning was performed immediately before gate oxidation to form a chemical native oxide. MOS capacitors with 3-6nm SiO2 gate oxides were used in the experiments to nvestigate the properties of gate oxides. Measured results of capacitors' electrical characteristics revealed that good GOI (gate oxide integrity) was gained and the average breakdown field was more than 11Mv/cm for 3-6nm SiO2 gate oxides prepared, which indicated little amount of metal or particle contamination in the Si/SiO2 system. Soft-breakdown occurred under CCS (constant current stressing) when the oxide thickness was less than 5nm. Discussion on the mechanisms of soft and hard breakdown was given in our analysis. And the influences of different gate oxide thickness, MOS capacitor areas and current stresses on the breakdown behavior were also discussed. .2. Nitrogen implantation into silicon substrate before gate oxidation was employed to obtain retarded oxidation rate. The effects of implant doses, annealing or not after implantation on gate oxide thickness control and reliability have been investigated. It has been found that there was a tradeoff between the amount of N concentration and gate oxide reliability. The higher implant doses gave better thickness control, but at the same time might cause degradation of gate oxide reliability. The samples that undergone thermal annealing (N2 ambient, 1000℃, 10s) had lower leakage current, higher average breakdown field than non-annealing ones because some structural damage induced by N2+ implantation could be annealed out. However, the retardation in oxide growth was more pronounced for the samples without such thermal annealing. .3. Nitrogen implantation into poly-Si electrode was performed to suppress boron penetration into the gate oxide and silicon substrate. In order to investigate the effects of implant energies, annealing or not directly after implantation on suppression of boron penetration and gate oxide reliability, characterization of the gate oxides was done by I-V, C-V, SIMS, SILC(stress induced leakage current) and reliability measurements at a consta

优化组合多晶硅后注N、NH3和N2O退火以及CoSi2/多晶硅栅电极结构和栅氧化后N2O快速退火等工艺，开发出抗硼扩散能力强、可靠性高2-7纳米超薄栅介质的工艺技术；探索其微观机恚桓慕?.8微米CMOS/SOI电路抗辐照性能及可靠性。本项目将对促进我国ULSI电路技术发展有重要作用。