设计验证一体化模拟版图自动综合技术研究

The back-end design of analog integrated circuit is an iterative, manual, error-prone, and time-consuming work as it needs take the effect of process variation into account. In the verification process for layout, density check is introduced alone as an important procedure to evaluate the variability of the vertical structure of each layer. Nowadays, with the introduction of 3-dimensional FinFET architecture, density check has become more significant to layout design. In order to essentially break the iteration of “design-verification” of analog layout to reduce the sign-off time, we propose a research project to develop an auto-placer for layout placement, which can generate the circuit layout and meanwhile synchronize with the verification of layout, i.e., integrate the design-verification cycles for the back-end design of analog circuit..This project covers two research aspects: (1) Using the C++ programming language to implement the algorithm of the auto-placer, which will perform “density- and design rule-aware” constraints-driven generation of elements and layout for the circuit, to verify the feasibility of the placer; (2) Investigating the characteristics of process variation to the circuit elements which are laid out by varying structures and styles, then building a mathematical statistics model of process variation by numerical fitting method, to improve the algorithm of layout synthesis with variation-suppression, and realize the feasibility and effectiveness. The success of this project, will fundamentally reduce the design iterations caused by the verification steps, improve the efficiency of the layout design, and eventually contribute to the technology of analog IC design automation of our country.

模拟后端设计需要考虑工艺波动的影响，是一个需要反复迭代、手动、易出错、耗时长久的工作。其中，在版图后端验证中，密度检测作为一个单独的环节被特别提出，以考察模拟IC各图层纵向结构的工艺波动。现今，随着3D FinFET架构的提出，密度检测的意义更加明显。为了从根本上打破模拟版图的“设计-验证”迭代，本项目创新研发一种可同步版图布局及其后端验证的布局器,巧妙实现设计验证一体化综合流程。该布局器论证涵括以下两方面:(1)基于C++编程，构建以密度检测和物理设计规则约束驱动的规则化器件布局算法，理论证明其可行性;(2)基于测试元件组(TEG)芯片提取多版图结构器件的工艺波动参数，采取数值拟合建立波动统计模型，以此改良算法并实现抗波动效应影响的版图综合,保证其合理性和有效性。预期本课题的成功，将从根本上消减版图验证引起的设计迭代，有效提升效率，为我国模拟集成电路设计自动化技术水平的提升做出贡献。

图论算法驱动的后端布图综合仍是实现模拟IC设计自动化的突破重点，终极目标是为设计者提供高效的点、线、面“布图-验证设计一体化”服务方案。从全球的EDA发展来看，我国在这一领域并不具备国际先进性。本课题正是为了解决这一“卡脖子”问题，针对复杂度更高的模拟IC自动综合技术进行研究，以实现国产工具的创新和替代。本课题核心技术点是，采用以等尺寸器件的规则阵列布局结合通道布线实现模拟IC的“布图-验证一体化”自动设计。截止目前，课题组已全部完成该综合系统的核心编程、开发和测试工作。以一个CMOS 90nm工艺模拟二级运算放大器的综合为例，自动设计结果与手工定制版图相比(定制在前)，在电气性能相近的条件下，设计时间(含物理验证)比为>4h V.S. 4s，电路面积比为1 V.S. 1.15，设计效率显著提升，应用效果良好。总结成果特色，体现在，1) 版图布局布线的规则性方便结合多种新兴智能算法实现高效设计组合，可进一步优化设计时间，程序可扩展性强；2) 器件矩阵生成和布线与版图DRC和密度检测验证同步完成，根除了传统的布图-验证迭代，提升了布图效率和人工操作正确率；3) 以FinFET为代表的3D架构器件的纵向工艺波动愈发敏感，器件规则阵列提高了电路平面工艺的薄膜材料的均匀性，抑制了工艺波动，为成品性能提供了保障。项目后期已完成二级运放、模拟延时器、带隙基准源、压控振荡器、电荷泵锁相环、模数转换器等多个模拟IC及系统级SoC的综合设计，各功能IP已签订协议，将于今年内完成实际流片及最终成品测试。从目前的后仿真分析以及工具运行情况来看，电路的电气性能指标均满足工程应用需求，工具的可操作性和实用性均符合预期，具备国内领先水平。