面向芯片间光互连的硅基高速全集成光接收机芯片研究

In the chip interconnection, since the electrical interconnection cannot meet the system requirement for the data rate of 100 Gb/s any more, the optical interconnection has become an inevitable trend to replace it. Currently hybrid integration is still the main approach to connect photonic devices with electronic devices for the CMOS optical receiver operating at the data rate of 100 Gb/s. In this approach, parasitic effects aroused from the bond pads and bond wires seriously restrict the frequency response and bandwidth of the optical receiver. SiGe BiCMOS process not only can implement fully monolithic integration of photodetector and front-end circuits of the receiver to eliminate the parasitic effects mentioned above through the local SOI technology, but also be compatible with large-scale CMOS circuits. Hence, it is necessary to carry out the key technique research on the 100 Gb/s monolithically integrated optical receiver with standard technology. In this project, the researches with the standard SiGe BiCMOS process are proposed as follows: 1, to design a waveguide-coupled PIN photodetector; 2, to design high-performance front-end circuits of the optical receiver at the single-channel rate of 25 Gb/s by low-power millimeter-wave methods; 3, to realize the optical receiver with the fully monolithic integration of the photodetector and front-end circuits, featuring the total data rate of 4 × 25 Gb/s. This project aims at providing the theoretical accumulation and technical solution for the development of optical interconnection for the fully integrated optical chips on the silicon substrate.

在芯片互连中，电互连已无法满足系统对100Gb/s速率的要求，光互连取代电互连已成为必然趋势。目前100Gb/s的CMOS接收机中光子和电子器件的互连还是以混合集成方式为主，该方式中由压焊盘和键合线所引起的寄生效应严重制约光接收机的频率响应和带宽。SiGe BiCMOS工艺既可以通过局部SOI技术实现光电探测器与接收机前端电路的单片全集成，以消除上述的寄生效应，又可以与大规模CMOS电路相兼容。针对用标准工艺实现100Gb/s的光电全集成接收机开展关键技术研究很有必要。本项目在SiGe BiCMOS工艺下拟开展以下研究：1、设计波导耦合的Ge型PIN光电探测器；2、采用低功耗毫米波技术来设计高性能接收机前端电路，单路速率为25Gb/s；3、实现探测器+接收机前端电路的单片全集成光接收机，速率为4×25Gb/s。本项目为硅基芯片间光互连的光电全集成芯片的发展提供理论积累和技术解决方案。

在芯片互连中，电互连已无法满足系统对100 Gb/s速率的要求，光互连取代电互连已成为必然趋势。目前100Gb/s的CMOS接收机中光子和电子器件的互连还是以混合集成方式为主，该方式中由压焊盘和键合线所引起的寄生效应严重制约光接收机的频率响应和带宽。因此光电探测器与接收机前端电路的单片全集成是实现100 Gb/s光互连中的重大挑战，也包含了很多的科学问题。本项目面向高速片上光互连的需求，围绕光电探测器和接收电路的融合和协同设计，开展高速光电全集成接收机芯片的原创性研究。通过标准硅基CMOS/BiCMOS工艺实现单路速率为25Gb/s的单片全集成光接收机，为研制4路并行速率为100Gb/s光接收机打下坚实的基础。本项目获得的主要结果体现在几个方面：在工艺与器件方面，研究在超高速工作环境下无源器件之间，无源器件和硅衬底之间的电-热-磁耦合效应以及寄生效应，建立包含温度效应的毫米波无源器件模型；基于这些无源器件模型，对传统的电路设计技术进行改进，本项目提出了多种对电路特性进行补偿的方案，设计出可对抗工艺偏差或者工作条件变化的模块与子系统；从工程实现的角度，本项目也对光接收机系统进行整合并通过流片验证与测试。本项目中流片验证了多款高性能的芯片，其测试性能指标在带宽和灵敏度技术指标等全面领先。例如采用0.25μm SiGe BiCMOS工艺实现的25Gb/s、4通道光接收机，在误码率为10^(-12)的条件下，其跨阻增益为63.17dBΩ，带宽为20.7GHz，灵敏度为-10.3dBm，输出摆幅为352.7mV，整个光接收机的功耗为111.6mW，芯片面积为0.086mm2。本研究具备重要的科学价值，实现了从器件特性研究到电路设计优化、再进行系统全面优化的创新。其中包含了硅基工艺特性研究、电磁兼容性、集成电路设计方法学、光通信技术等多学科的融合创新。本项目的研究为硅基芯片间光互连光电集成芯片的发展提供理论积累和技术解决方案。