纳米工艺下SoC电源/地网络分析及验证方法

With the manufacturing technology has been into nanometer era, it ensures smaller size, higher integration and lower power consumption. Meanwhile, the significantly parasitic effects, the increasing design scale and the reducing voltage tolerance are making the analysis of power/ground (P/G) RLC network as bottleneck for very large scale SoC design. This will affect the chip performance, power consumption and yield which is a hot topic of both research area and industrial world. In order to ensure the robustness of power network on chip, we must solve the challenging problem of the P/G analysis of accuracy, run efficiency and memory consumption. This project will research the analysis methods of RLC network for large scale complex structure P/G network design. From the geometric structure of P/G network, package inductance parameters and problem characteristics, we study the P/G RLC modeling and reduction methods to provide a basis and guidance to improve analysis efficiency and resources consumption. And based on above we perform in-depth study on P/G transient analysis of equation of state of nature, frequency response and solving methods to improve the analysis performance which can reduce the time and space complexity without accuracy loss. We will also research vector-less verification methods for early stage P/G verification which can provide design references without input stimuli of circuit cells. Based on the characteristics of P/G structure and linear solvers we will research parallel algorithms and acceleration strategies to improve the analysis efficiency. This project will provide strong supports of basic theories and algorithms for SoC P/G design which will play an important role in theoretical research and practical use.

集成电路进入纳米时代，电源/地网(P/G)电流增大、寄生效应显著和电压降容限降低，成为严重影响芯片性能、功耗和可靠性的设计瓶颈。SoC芯片规模和复杂度的增大，使电源/地网分析和验证面临规模、精度、效率和内存资源的巨大挑战，是业界研究和亟待解决的热点问题。本课题针对SoC中P/G设计存在的问题，深入研究P/G网络快速分析方法。从P/G结构、封装电感特性及求解问题规模入手，研究P/G电阻、电容和电感建模和约简方法，为提高分析效率和减少资源占用提供基础及指导；在此基础上深入研究P/G瞬态分析方法，通过对方程性态、频率响应和求解方法的研究，提高分析精度和效率；研究非向量输入P/G验证方法，在设计早期无法获得模块吸纳电流情况下，为供电系统设计提供参考依据；依据P/G结构特点和求解算法的特性，研究并行加速算法和策略，提高分析效率。课题将为SoC供电设计提供理论和算法支撑，具有重要理论研究和实用价值

随着集成电路工艺进入纳米阶段，电路寄生效应更加显著，大规模片上供电网络设计与分析更加复杂，SoC供电网络分析面临巨大挑战。本课题重点研究和探讨了纳米工艺下集成电路设计中的供电网络的快速分析验证问题，课题围绕纳米工艺下的片上供电网络的建模、快速瞬态分析、无向量早期验证和供电网络信息安全等问题开展了研究，提出和建立了纳米工艺下大规模复杂供电网络的相关模型和参数计算方法；在此基础上提出了一系列供电网络高效而稳定的分析和验证的算法，包括：基于结构的大规模复杂供电网络的建模方法、基于泊松预条件的非结构化的供电网络快速分析算法、基于电路拓扑划分的分块并行仿真供电网络快速瞬态噪声分析方法、多级层次式矩阵求逆算法、基于局部性原理的选择性矩阵求逆算法、基于最大电压降预置的无向量验证方法，等等。本课题在以上算法研究的基础上，完成了软件原型的开发并通过实例测试。通过对片上供电网络分析验证的算法研究，为纳米工艺下的集成电路电源完整性设计提供了理论、研究方法和算法原型，进而为集成电路电源完整性设计EDA软件工具开发打下了理论和算法基础。