4H-SiC外延层中基面位错增殖的研究

Basal plane dislocation is the root cause of degradation of silicon carbide (SiC) bipolar devices. Multiplication of basal plane dislocations has to be avoided during the high temperature processes of SiC device fabrication, including epitaxy and ion implantation activation annealing. The applicant has achieved multiple original key findings on the basal plane dislocation multiplication during 4H-SiC epitaxy. Similar phenomenon during activation annealing has also been reported. However, it was quite different as compared to that in epitaxy and was little understood. The project will study the critical conditions for the basal plane dislocations to multiply during activation annealing, which will offer guidance to the processing of SiC devices. The project will also perform systematic observation and analysis on the microstructures of the interfacial dislocations produced by the basal plane dislocation multiplication, so as to explain the driving force and kinetics of the dislocation behavior. Finally, we will study the response of interfacial dislocations to electron and hole injection, and answer the questions of whether and how basal plane dislocation multiplication would affect the performance of SiC devices. We expect the above work to promote the transition of SiC power electronics from unipolar devices to 10kV and higher voltages bipolar devices.

基面位错是导致碳化硅双极型器件正向性能恶化的根本原因。碳化硅器件制备的高温工艺必须遏制基面位错的增殖，包括外延生长与离子注入后激活退火。申请人已在外延生长过程中的基面位错增殖现象上取得多项原创性成果，而离子注入后激活退火工艺所导致的基面位错增殖与前者有相似点，也有显著不同，业内对此了解甚少。本项目将研究碳化硅离子注入后激活退火过程发生基面位错增殖的临界条件与影响因素，为碳化硅器件工艺提供参考，并将结合已有研究基础，对增殖所产生的界面位错的微观结构进行系统研究与分析，以解释基面位错增殖的驱动力和动力学。继而，将对界面位错在电子空穴注入条件下的响应进行研究，确定不同类型界面位错对碳化硅器件性能的影响。以上工作将弥补业内对碳化硅器件工艺可能导致的基面位错密度增加关注不够和对碳化硅外延层内基面位错微观结构的认识有限这两点不足，促进碳化硅电力电子从单极型器件向10千伏及以上双极型器件的推进。

基面位错是导致碳化硅双极型器件正向性能恶化的根本原因。离子注入后的激活退火是碳化硅器件制备必不可少的高温工艺，必须遏制其可能发生的基面位错增殖。本项目对4H-SiC外延层中N、Al离子注入造成的晶格应变及高温退火后应变的演变进行了系统的测量与分析，研究了不同注入剂量、是否图形化对应变的影响，并探测是否出现了BPD的滑移与增殖、是否产生界面位错。进而对界面位错的微观结构进行了表征，并分析了其在电子空穴注入条件下层错扩展的可能性。基于实验结果提出了离子注入4H-SiC及退火过程的应力/应变模型，并基于此分析了产生界面位错的必要条件。以上科研成果为业内首次对4H-SiC中离子注入高温退火导致BPD增殖的机理的系统研究。从应用角度来看，由于商业4°斜切4H-SiC外延片内的BPD密度已经能够控制到1 cm^-2以下，并且高剂量的N、Al离子注入采用高温注入降低对晶格的损伤，因此目前4H-SiC电力电子器件制备过程中的离子注入和高温退火工艺在产生界面位错方面是安全的。然而由于4H-SiC外延层中的典型界面位错皆可能引发电子空穴注入条件下的层错扩展、导致双极型退化，因此需要在4H-SiC电力电子器件的生长和制备工艺中避免。