基于TSV测试与容错的3D芯片良率提升方法研究

The 3D technology is an important technique to transcend Moore's law, but the yield and cost are the main obstacles for the commercial application of 3D chips. Researches show that the TSV defects will cause the yield of 3D chips much lower than expected. This research focuses on the yield enhancement of 3D chips based on the TSV test and fault tolerance methods. The main contents include: (1) TSV testing based on vernier method. It can test TSV with high precision, classify TSVs through quantitative analysis, and eliminate some potential TSV failure in the early stage so as to enhance the yield of 3D chips. (2) Double-TSVs online self-tolerance scheme. This scheme avoids the timing overhead due to the complex reconfigurable circuits, and realizes the online TSV fault self-tolerance to enhance the yield of 3D chips. (3)TSV fault tolerance optimization method under timing constraints. By properly adding redundant TSVs, it can achieve cost optimization under timing constraints, and thus enhance the yield of 3D chips. This research can effectively improve the yield and reduce the cost of the 3D chips, which is of great significance to promote the commercial development of 3D chip,and has a strong theoretical and practical importance.

3D技术是超越摩尔定律的一项重要技术，但良率和成本却是限制3D芯片商业应用的主要障碍。研究表明，TSV缺陷将会造成3D芯片良率远低于预期。本课题以基于TSV测试与容错的3D芯片良率提升方法为切入点，主要内容包括：（1）基于游标法的TSV测试方法。实现高精度的TSV测试，通过量化分析TSV故障程度对TSV进行分类，在较早阶段消除一些潜在的TSV故障，从而提升3D芯片良率；（2）双TSV在线自容错方案。避免复杂重配置电路带来的时序开销，实现TSV的在线自容错，以提升3D芯片良率；（3）时序约束下的TSV容错优化方法。通过合理地添加冗余TSV，实现时序约束下的成本最优化，进而提升3D芯片良率。本研究可以有效提升3D芯片的良率，促进3D芯片的商业化发展，具有很强的理论和现实意义。

本项目主要研究了超越摩尔领域中3D IC的测试与容错等关键技术，以优化3D IC良率和成本。本项目在3D TSV的故障测试、TSV故障在线自容错、时序约束的容错优化方面取得多项创新性成果：.（1）测试方法上，提出堆叠顺序的测试时间优化、基于延时的低成本TSV缺陷测试、使用机器学习的测试模式优化技术、预测X值输入的灵敏度等，优化测试成本，提高测试覆盖率。.（2）基于小延时的测试方面，提出基于RO的小延时测试、基于游标环的绑定前TSV测试、PUF映射单元的稳定性测试、基于传输线的测试，提高测试分辨率。.（3）时序约束的TSV容错优化方法方面，提出温度感知的3D IC布局、TSV冗余容错架构，时分复用的容错架构，实现低开销、高故障覆盖率的故障容忍，提高3D芯片可靠性。.（4）在TCAD、TCAS、Chinese Journal of Aeronautics、TVLSI、IEICE、计算机辅助设计与图形学学报、ITC-Asia、ISCAS等国内外著名期刊和会议上共发表学术论文59篇，其中SCI收录25篇， EI收录18篇；共申请发明专利43件，其中已授权发明专利22件；培养出5名博士和20名硕士，在读博士研究生7人与硕士研究生10人；成功举办第27届IEEE亚洲测试学术会议(IEEE 27th Asian Test Symposium，简称ATS'2018)；成功举办第19届IEEE寄存器传输级及高层测试国际研讨会(简称WRTLT'2018)。