表面电极离子阱芯片可扩展设计研究

Ion trap quantum computing system ranks the top since the merits of long coherence time, logic operation with higher fidelity, and so on. Nowadays, scalable surface-electrode (SE) ion trap is an effective scale approach. However, SE ion traps is known to be limited with regard to trap depth shrinking, the traditional analysis of anharmonic axial potential is not accurate enough to guide such trap design, junctions in two-dimensional ion traps are hard to optimize, and the uncertainty of demand for long ion chain separation, and so on. The situation goes worse with SE ion trap experiments has moved to large-scale demonstration. To address this issue, a systematic analysis of the underlying reason is recommended. In this project, we will propose electrostatics of SE ion traps with top electrode, quantitative model to guide anharmonic chips design, flexible method to optimize the junctions and a new method to control split of large-scale ion chain, to address the bottleneck issues respectively. Furthermore, in order to verify the correctness of the design rules, ion trap chips will be fabricated according to the design rules obtained from the theory studies, our project has both significant strategic importance and applicable vaule.

离子阱量子计算物理系统以其相干时间长、逻辑操作保真度高等优势，成为量子计算物理系统研究的热点。目前，可扩展离子阱芯片被认为是实现大规模离子量子计算的有效途径。然而，离子阱芯片可扩展研究正面临势阱深度锐减、非谐理论不适合非谐单阱设计、多阱连接处“结”区射频电极形状优化难、长串离子分离操作对芯片结构需求不明朗等挑战，特别是离子量子计算已经从小规模实验演示过渡到大规模可扩展的今天，上述挑战已经成为亟待解决的关键问题。为此，本课题立足问题的本源，提出离子阱芯片加盖的理论、非谐势离子阱芯片量化分析模型、灵活的“结”区射频电极优化设计方法以及面向长串离子分离的芯片电极优化设计方法，对关键瓶颈进行各个击破。在理论成果指导下制备表面电极离子阱芯片，验证所提模型和方法的正确性和实用性，具有重要的战略意义和应用价值。

离子阱量子计算物理系统以其相干时间长、逻辑操作保真度高等优势，成为量子计算物理系统研究的热点。目前，可扩展离子阱芯片被认为是实现大规模离子量子计算的有效途径。然而，离子阱芯片可扩展研究正面临势阱深度锐减、非谐理论不适合非谐单阱设计、在半导体硅基衬底材料上离子加热率大设计等挑战，特别是离子量子计算已经从小规模实验演示过渡到大规模可扩展的今天，上述挑战已经成为亟待解决的关键问题。为此，本课题立足问题的本源，提出离子阱芯片加盖的理论、非谐势离子阱芯片量化分析模型以及从高频器件结构设计和电极纳米加工角度分析离子阱芯片对材料的需求，对关键瓶颈进行各个击破。在理论成果指导下设计制备了一款表面电极离子阱芯片，并取得了较好的实验测试效果，验证所提模型和方法的正确性和实用性。