高速低压长保持力GaAs MOS为基量子点非挥发性存储器研究

The project aims at small-scalled GaAs MOS-based quantum dot (QD) nonvolatile memory with high speed, low operating voltage and long retention. A new stacked gate structure of Al-HfO2-InxGa1-xAs(QD)-HfO2-GaAs is proposed and prepared, where fabrication technologies of the InxGa1-xAs QD and determination of optimal tunnel-layer thickness are key research contents. The optimal tunneling and blocking barriers are obtained through embedding the undoped InxGa1-xAs QD into HfO2 and adjusting In content to a suitable value so that the optimal QD charge traps and reasonably thinning of the tunnel layer can be realized to reduce operation voltage and enhance programming/erasing speed. A large memory window is achieved to realize multi-level memory by optimizing QD size and distribution. A small equivalent oxide thickness of the tunnel layer can be gotten by designing a large physical thickness due to large k value of HfO2 so that both high operation speed and good retention can be obtained. The interface properties of the HfO2/GaAs is improved and the Fermi-level pinning is eliminated by depositing TaON as interfacial passivation layer. The optimal technologies and conditions of fabricating the stacked gate dielectrics and InxGa1-xAs QD will be investigated by using MOCVD method, and the prototype sample of the relevant GaAs QD memory is prepared. It is expected that the size of the new type of GaAs MOS-based QD memory can be scaled to below 10 nm due to effective combination of the InxGa1-xAs QD with high-k HfO2 dielectric.

以高速低压长保持力GaAs MOS为基量子点(QD)非挥发性存储器为研究目标，设计制备新型Al-HfO2-InxGa1-xAs(QD)-HfO2-GaAs栅堆栈结构，重点研究InxGa1-xAs量子点的制备技术及最佳隧穿层厚度的确定。通过将未掺杂量子点嵌入HfO2并调整In含量至合适值来获得最佳隧穿势垒和阻挡势垒，以实现最佳量子点电荷陷阱及隧穿层的合理减薄，达到降低工作电压、提高编程/擦除速度之目的；通过对量子点尺寸及分布最佳化，获得大的存储窗口，以利于多值存储。由于HfO2高的k值，可设计较大物理厚度获得小的隧穿层等效氧化物厚度，使工作速度提高的同时，获得好的保持力；通过淀积TaON钝化层改善界面特性，消除费米能级钉扎。将研究MOCVD制备量子点和栅介质的最佳工艺和条件, 研制出相应的GaAs量子点存储器原型样品。由于量子点与高k介质的有效结合，有望使器件工艺节点等比缩小到10nm以下。

以高速低压长保持力GaAs MOS为基量子点(QD)非挥发性存储器为研究目标，具有存储功能的新型栅堆栈结构已制备完成，重点研究了量子点的制备技术及最佳隧穿层厚度的确定。通过对GaAs界面的钝化处理改善界面特性，消除费米能级钉扎，获得最佳的界面特性以实现隧穿层的合理减薄，达到降低工作电压、提高编程/擦除速度之目；通过对量子点制备工艺的优化，实现尺寸及分布最佳化，获得大的存储窗口，以利于多值存储；采用高k介质材料对隧穿层、量子点存储层以及阻挡层进行材料选择与能带设计，获得最佳隧穿势垒和阻挡势垒，可设计较大物理厚度获得小的隧穿层/阻挡层等效氧化物厚度，使工作速度提高的同时，获得好的保持力；研制出了相应的GaAs量子点存储器电容原型样品。由于量子点与高k介质的有效结合，有望使器件工艺节点等比缩小到10nm以下。