抗控制流攻击的硬件扰乱模型及VLSI实现

Control Flow Attack (CFA) has become a great threat to the security of information systems. In order to destroy the system or steal important data, CFA usually uses the control flow vulnerability to make the system to execute some pre-defined malicious codes, especially by tampering with the data, status or instruction set. By the way of changing circuit’s structure or storage mode to disorder the presentation of internal data, hardware disruption can be employed to resist Return Oriented Programming (ROP), Jump Oriented Programming (JOP) and Counterfeit Object Oriented Programming (COOP). Therefore, the hardware disruption model will be constructed in this project for revealing the inherent relationship between vulnerabilities and hardware defects. Through capturing disturbance nodes in control flow and establishing reasonable hardware disturbance recovery mechanism, the project will lay stress on the mitigating control flow attack VLSI design techniques. The research includes the mechanism and model construction of hardware disruption, hardware disruption of disordered data storage and state transition, hardware disruption of the random security processor instruction set and performance evaluation of hardware disruption. The research results are expected to provide scientific theory and methodology for mitigating control flow attack in VLSI design and promote the development of security chips.

控制流攻击(Control Flow Attack, CFA)利用系统控制流漏洞，通过篡改控制流的数据、状态和指令集等方式，诱导并执行预先设定的恶意代码，达到破坏系统或盗取关键数据的目的，已经对信息系统的安全性构成极大威胁。硬件扰乱指通过改变电路结构或存储模式扰乱控制流内部数据的呈现形式，可以有效防御返回程序、跳转程序和假冒对象程序等控制流攻击。鉴此，本项目旨在通过控制流攻击机理的研究，揭示控制流漏洞和硬件缺陷的内在关系，构建硬件扰乱的数学模型，捕获控制流的硬件扰乱结点，建立合理的硬件扰乱恢复机制，提出有效的硬件抗控制流攻击VLSI设计方法。主要研究内容包括：硬件扰乱机理和模型构建，数据存储和状态跳变无序化的硬件设计，指令集随机化安全处理器的硬件实现，抗控制流攻击性能评价与优化等。研究成果将为抗控制流攻击的VLSI实现提供科学的理论依据和方法指导，推动高性能安全芯片的广范应用。

本项研究旨在通过对芯片抗控制流攻击机理的研究，揭示控制流漏洞和硬件缺陷的内在关系，构建硬件扰乱的数学模型；提出捕获控制流中硬件扰乱结点的有效方法，确定扰乱结点的数量和位置，解决扰乱效果与硬件开销平衡、过度扰乱等问题；建立有效的数据、状态和指令集恢复机制，保证系统在扰乱后正确、稳定、高效地运行；实现高鲁棒性PUF电路、高安全性状态混淆嵌入式处理器、低开销指令集随机化和编译器硬件化、可兼容的内置安全寄存器组等VLSI方案；搭建可信测试平台，通过理论和实验相结合的方法评价所提方案。本项目课题组已顺利完成既定内容的研究。项目研究期间发表学术论文49篇，其中期刊论文35篇，会议论文14篇；授权发明专利4项；授权集成路布图登记6项。项目研究期间，1名副教授职称晋升为教授职称，1名讲师职称晋升为副教授职称，培养硕士生12名。相关技术已得到应用，部分成果获得全国大学生集成电路创新创业大赛一等奖1项、“华为杯”中国研究生创芯大赛二等奖1项、三等奖5项等。研究成果将为抗控制流攻击的VLSI实现提供理论依据和方法指导，推动高性能安全芯片的广泛应用。