面向静态功耗优化的SRAM型FPGA布线算法研究

As the feature size of SRAM-based FPGAs shrinks to the nanometer scale, static power has surpassed dynamic power, being the dominant part of the FPGA power. Such trend will become more prominent along with smaller feature size. Prior FPGA routing works have invistigated how to co-optimize static power, delay and wire conjection. However, existing algorithms only target the on-path static power,leaving the off-path static power issue not addressed. This project focuses on the static power reduction of SRAM-based FPGAs, including of (1) proposing an accurate static power model. By analyzing the structure characteristics of FPGA routing resources that FPGA wires have tremendous amount of off-path transistors, our model considers the off-path transistors' static power hence can accurately and efficiently estimate static power of the FPGA chip; (2)based on the accurate analysis model of static power, proposing novel low off-path static power routing algorithms; (3) analyzing the temperature effect on static power and delay, and then proposing temperature-aware routing algorithms to reduce static power. This project will conduct experiments on commercial SRAM-based FPGAs, develop prototype routing tools, and provide key techniques of low power design for future SRAM-based FPGAs.

随着SRAM型FPGA芯片的工艺特征尺寸进入纳米尺度，静态功耗已经超越动态功耗，成为芯片功耗的主要组成部分，并且，随着特征尺寸的进一步减小，该趋势还将更加显著。尽管已有FPGA布线方面的研究工作初步探讨了静态功耗、时延和拥塞度的协同优化，但由于仅针对通路静态功耗进行优化，导致优化效果欠佳。本项目针对SRAM型FPGA芯片的静态功耗，研究以下三方面内容：（1）建立准确的静态功耗分析模型。深入讨论FPGA连线具有大量"旁路晶体管"的结构特性，并将旁路静态功耗纳入建模，对全芯片静态功耗进行准确快速评估；（2）在第一项工作的基础上，提出考虑旁路静态功耗的布线算法；（3）深入分析温度效应导致的静态功耗和时延波动，提出考虑温度效应的低静态功耗布线算法。本项目将结合实际SRAM型FPGA芯片的电路结构与设计流程开展实验，研制相应的布线工具原型，为未来SRAM型FPGA的低功耗设计提供有效方法和关键技术。

随着SRAM 型FPGA 芯片的工艺特征尺寸进入纳米尺度，静态功耗已经超越动态功耗，成为芯片功耗的主要组成部分，并且，随着特征尺寸的进一步减小，该趋势还将更加显著。本项目针对SRAM 型FPGA 芯片的静态功耗问题，研究了静态功耗分析模型，提出了考虑旁路静态功耗的布线优化算法和逻辑模块配置比特翻转算法；深入分析了温度效应导致的静态功耗和时延波动，提出了考虑温度效应的布局算法；提出了基于热能功耗容量估算模型的热能功耗管理方法。本项目结合实际SRAM型FPGA芯片的电路结构与设计流程开展了实验，研制了相应的布线工具原型，为未来SRAM型FPGA的低功耗设计提供了有效方法和关键技术。