基于势阱形式控制的半导体/绝缘层复合薄膜电容器设计与特性研究

Energy storage capacitors have been attracting a growing attention due to their extensive applications in electric automobiles, clean energy sources and grid-connected systems. For a nanolaminate-film capacitor composed of alternative semiconducting(S) and dielectric insulating(I) layers, the doped semiconducting layer is expected to enable electrons to act as polarization charges, which is significant for the improvement of charging/discharging rates. On the other hand, the type of potential well induced by the I/S/I structure is responsible for the interfacial distribution of electric potential. A nonuniform distribution causes a dielectric breakdown, which can be effectively avoided by tuning the type of potential well according to our preliminary theoretical study, leading to an increase of working voltage limit. This proposal will apply atomic layer deposition method to realize a nano-scaled structure unit composed of Al2O3/AZO/ZnO/AZO/Al2O3 as well as the alignments of a few of the unit to produce nanolaminate-film capacitors. The interface structure of the capacitors is investigated with varying parameters such as carrier concentrations of the doped semiconductor layer, each sublayer thickness of the system and so on. The dielectric characterizations including permittivity and working voltage are studied in detail in correlation with different types of the potential well depending on the interfacial potential distributions, in an attempt to offer a theoretic and technical support to achieve a high-performance multilayer capacitor system with large capacity amount, high working voltage limit as well as rapid charging/discharging rates.

电动汽车、清洁能源发电并网等领域迫切需要发展具有大电容量、高工作电压、快充放电速率的高性能复合薄膜电容器。针对由半导体层与电介质绝缘层构成的复合薄膜电容器，通过在半导体层中注入电子作为主要介电极化电荷，并结合界面处势阱形式的调控，可同时提高复合薄膜介电常数与高频特性，抑制局部电场过大导致的局部击穿，提高工作电压。本项目提出并拟采用ALD法制备以绝缘体(Al2O3)/掺杂半导体(AZO)/本征半导体(ZnO)/掺杂半导体(AZO)/绝缘体(Al2O3)形成的纳米多层结构作为结构单元，并将其在厚度方向反复叠加形成复合薄膜电容器，研究不同成分和结构的掺杂半导体层特性以及各层厚度等结构参数对势阱形式和电容特性的影响机制，揭示掺杂半导体层对极化电荷数量、迁移特性和势阱形式的调控机理以及势阱形式对工作电压的影响规律，建立对极化电荷和界面势阱形式的调控方法，为发展高性能复合薄膜电容器提供理论与技术支撑。

本课题采用原子层沉积(ALD)法制备Al2O3/ZnO(AZ-NLs)纳米多层复合薄膜，研究了ALD法沉积多层膜的工艺；揭示了各子层厚度、相对比例、组元性质和界面状态对纳米多层复合薄膜结构形貌和介电性能的影响规律及其内在机理，获得了具有高介电常数、良好的频率/温度稳定性和优异储能特性的复合薄膜。研究发现AZ-NLs纳米多层膜介电常数相比其组元本征介电常数显著增加，且可通过改变ZnO、Al2O3子层厚度在50~3000范围内进行调节，这是由于I型带阶结构的ZnO/Al2O3界面引起的载流子界面极化所导致。针对复合多层膜的介电频率特性的研究表明，AZ-NLs薄膜具有Debye型弛豫特征，当频率上升至某一截止频率处时，介电常数出现台阶式下降，该截止频率取决于极化电荷弛豫速度，并随不同子层厚度在102~106 Hz之间变化。子层厚度对介电温度特性也有很大影响，当ZnO厚度小于20 cycles时，介电常数在温度降至某一临界值时同样出现台阶式下降，且ZnO厚度减小或Al2O3厚度的增加均使临界温度上升，这是由于量子限制效应增强引起的能带分裂导致电荷弛豫激活能增加所造成的。在上述研究基础上对纳米多层复合薄膜进行结构优化，当ZnO和Al2O3子层厚度分别为14和4 cycles时，复合薄膜具有高达800的室温相对介电常数(1kHz)，且在77~380K、102~106Hz范围内，介电常数变化小于12%，具有良好的温度/频率稳定性。同时，AZ-NLs纳米多层复合薄膜具有线性极化特征，室温介电强度为2.5 MV/cm，储能密度达140 J/cm3。