基于电流模式的能量测量像素读出芯片设计和架构的研究

As the exploration to the matter world steps deeper and further, the requirement of the detector performance is getting increasingly higher. Because of its good resolution, ultra low noise, and high counting rate tolerance, pixel detector has become the indispensable core technology in future high energy physics and radiation imaging applications. In order to fill the gaps of the extensive application of pixel detectors in domestic high energy physics field, it is the trend to master the design techniques of pixel readout chips. Different from readout chips for conventional detectors, as they are ordinarily designed on mature VLSI technologies, the design of pixel chips always tends to apply advanced ones represented by the 0.13μm technology. Therefore the integration can be improved and the pixel size can be shrunk. However, the power supply voltage will significantly decrease as the feature size of the technology gets smaller. This leads to a serious challenge to the analog circuits' design, which is based on the conventional voltage mode. Focusing on breaking through this design bottleneck, we will study the pixel front-end circuits based on current mode, with a premise of preserving the performance. Thus the circuit can get rid of the restrictions of low power supply voltage, and its static power dissipation can be greatly saved. This design is also expected to propose a reference for readout chips of other conventional detectors, when the advanced technologies are finally taken advantages of in the recent future. Additionally, we are trying to study the in-pixel energy measurement on the basis of our early research, and to implement a high resolution, low power consumption energy measurement of a single particle.

随着对物质世界探索的不断深入，人们对探测器性能的需求越来越高。像素探测器以其高分辨率、极低噪声和高计数率工作能力，成为未来高能物理实验和辐射成像应用中不可或缺的核心技术。为填补国内高能物理领域像素探测器大规模应用的空白，掌握像素读出芯片设计技术可谓大势所趋。不同于常规探测器读出芯片通常采用较为成熟的集成电路工艺，像素芯片设计总是趋向于采用以0.13μm工艺为代表的先进工艺，从而不断提高集成度，缩小像素尺寸。工艺特征尺寸的降低将导致电源电压的显著下降，这对传统基于电压工作模式的模拟电路设计提出了严峻挑战。针对这一设计瓶颈，本项目将在保证电路性能的前提下，研究基于电流模式的像素前端电路，试图摆脱低电源电压的限制，从而突破设计瓶颈，大大降低芯片的静态功耗，并为未来采用先进工艺的其他探测器读出芯片提供参考。在前期研究的基础上本项目还将研究像素内能量测量功能，完成高精度、低功耗的单粒子能量测量。

随着对物质世界探索的不断深入，人们对探测器性能的需求越来越高。像素探测器以其高分辨率、极低噪声和高计数率工作能力，成为未来高能物理实验和辐射成像应用中不可或缺的核心技术。为填补国内高能物理领域像素探测器大规模应用的空白，掌握像素读出芯片设计技术可谓大势所趋。不同于常规探测器读出芯片通常采用较为成熟的集成电路工艺，像素芯片设计总是趋向于采用以0.13μm 工艺为代表的先进工艺，从而不断提高集成度，缩小像素尺寸。工艺特征尺寸的降低将导致电源电压的显著下降，这对传统基于电压工作模式的模拟电路设计提出了严峻挑战。. 针对这一设计瓶颈，本项目在保证电路性能的前提下，将基于电压模式的像素单元电路全面改进为基于电流模式的电路，一方面简化了电路结构，另一方面也显著节省了电路面积，并且电路结构不受低电源电压的限制，突破了电压模式电路的设计瓶颈。在此基础上本项目还完成了像素单元内能量测量功能，并且完成了单元内模数变换功能。通过在数据读出结构中引入零压缩，使得芯片每像素单元计数率可以超过100kHz。. 通过本课题的研究，掌握了基于电流模式的前端电路的设计方法，并且提出了基于电流模式的像素芯片能量测量与数据读出的架构，为其他同类芯片的设计研究提供了有益参考。