逻辑级破解纳米集成电路软错误可靠性评估难题的新方法

Nanoscale integrated circuits are very susceptible to radiation. The soft errors induced by high energetic particles affect the circuit reliability severely. An accurate reliability evaluation about soft errors in integrated circuits can guide the circuit synthesis and tolerance design efficiently, which is a hot research spot in academia and industry. However, most existing evaluation methods are only suitable for the cases of one-cycle, single-fault, medium or small scale integrated circuits, which can hardly balance the accuracy and efficiency. This proposal attempts to propose new methods to resolve these difficult problems for the circuits at logic level. Our research work will mainly focus on the propagation probability analysis of transient pulse, the reliability calculation in continuous clock cycles, the reliability target decomposition and evaluation affected by multiple transient faults and the optimization of fault simulation algorithms. Moreover, our key research ideas are as follows. First, the transient pulse propagation characteristics in continuous cycles will be analyzed based on the representation and the union operation of transient pulse propagation probability matrices (TPPM). Next, the evaluation target of circuits affected by multiple transient faults will be decomposed to fault-free component, principle component and high-order components. Then, we will focus on the principle component and the primary high-order components. Finally, the simulation algorithm will be optimized and the evaluation efficiency will be enhanced substantially by calculating the faults propagation metrics through two topological traversals of the circuit at logic level. All in all, this proposal will provide effective solutions for reliability evaluation of multi-cycle, multi-fault and VLSI circuit greatly, which has much important research significance and application value.

纳米集成电路对辐射异常敏感，因高能粒子轰击引发的软错误严重影响着电路的可靠性。准确评估集成电路的软错误可靠性能有效指导电路综合与容错设计，是学术界和工业界关注的热点，但现有多数方法仅仅适用于单周期、单故障和中小规模的电路评估，且难以兼顾准确与高效。本课题从电路逻辑级入手研究破解这些难题的新方法，主要研究内容包括：瞬态脉冲传播概率分析、连续周期可靠性计算、多故障电路可靠性目标分解与评估及故障模拟算法优化。关键思路是以脉冲传播概率的矩阵表示与并积运算为基础分析连续周期故障传播特性；将多故障电路的评估目标分解为零故障直流分量、一阶主分量与高阶分量之和，聚焦主分量与主要高阶分量；在逻辑级通过正反两次遍历电路计算故障传播度量值，优化模拟算法，大幅提高可靠性评估效率。本研究将在很大程度上为多周期、多故障和超大规模的电路可靠性评估提供有效解决方案，具有重要的研究意义和应用价值。

随着纳米工艺的应用，集成电路规模不断增大，器件特征尺寸持续缩小，芯片性能得到提升，但与此同时，因各种辐射导致的软错误也给芯片的可靠性带来了严峻挑战。本项目针对纳米集成电路受软错误影响时的可靠性问题，研究现阶段极具现实意义的连续时钟周期、多瞬态故障影响和超大规模的电路可靠性评估方法。具体研究内容及成果包括：1、提出一种新的单粒子瞬态故障传播概率分析方法，将逻辑屏蔽、电气屏蔽与时钟窗口屏蔽三种故障屏蔽效应统一考虑，并使用瞬态故障传播概率矩阵表示四种类型的故障脉冲传播概率，结合矩阵并积运算，大大简化了多周期的可靠性计算，提高了评估效率，使逻辑电路工作于连续时钟周期的可靠性评估具有实际意义；2、提出基于概率分布模型的逻辑电路软错误可靠性评估方法，将多瞬态故障影响下电路的可靠性目标分解为零故障直流分量，一阶主分量与高阶次要分量之和，并将研究重点集中到主分量与主要高阶分量的计算，结合概率统计的分析方法，有效解决了多故障电路可靠性评估难题；3、提出基于故障传播度量的逻辑级分析方法，大大简化了故障模拟过程，在保证准确性的前提下，将各种逻辑级评估方法的应用对象从现阶段的千门量级逻辑电路提升至万门甚至更大规模电路；4、提出电路相关性分离方法，在现有工艺条件下可解决因扇出重汇聚结构引发的信号相关性问题，且耗时少，准确性高，并将此方法用于逻辑电路可靠性评估，以及低成本、高效率的容软错误设计。综上，本研究对于集成电路逻辑综合与容软错误设计的发展具有重要意义，研究成果能为可靠性增长提供量化标准，为高可靠性电路的综合与设计提供新的方法和关键技术，具有重要的理论意义和应用价值。后续工作是继续开展电路相关性分离方法的研究；并对失效率敏感的输入向量与逻辑单元进行准确定位，为低成本容错设计提供参考依据，促进电路容错设计的发展。