基于Sb掺杂p-ZnO/n-ZnO同质结纳米线的压电光电子学效应布尔逻辑器件研究

The Boolean logic devices integrated by ZnO nanowire (NW) ultraviolet -light-strain-gated-transistor (LSGT) will have broad application prospect in wearable electronics. The extra concentration of the free electrons in ZnO NWs caused piezoelectric potential screening effect and excess energy consumption. And due to interface defects induced by lattice mismatch of the ZnO-based heterojunction, the modulation capability of the piezoelectric potential to the bandgap structure is reduced. So it is a challenge to obtain the Boolean logic devices with high sensitivity, low power consumption, and integration. In this project, we propose to obtain the p-ZnO:Sb/n-ZnO homojunction NWs with the optimal concentration doped by chemical vapor deposition method. The p-n homojunction NWs have depletions with low carrier concentration and matched lattice interfaces, so they provides a material platform for solving the problems of piezoelectric potential screening effect and interface defects. Then the p-n homojunction LSGT device will be fabricated, where the high performance Boolean logic devices, such as half adder, half subtractor, full adder, and full subtractor will be integrated. The screening effect of the piezoelectric potential and the energy consumption of the device can be reduced by forming p-n homojunction, which will modulate the electrical transport properties of the ZnO NWs. The photo-sensitivity and pressure-sensitivity performance of the Boolean logic device will be enhanced enormously. This work will provide the theoretical and experimental basis for developing ZnO-based logic devices, including materials preparation, carrier transport, and piezoelectric potential screening effect.

ZnO纳米线紫外光-应变双门控晶体管（LSGT）集成的布尔逻辑器件在可穿戴电子设备领域具有广阔的应用前景。然而，本征ZnO纳米线内部过高的自由电子浓度导致压电势屏蔽效应和高能耗的问题，及ZnO基异质结中晶格失配造成的界面缺陷减弱了压电势对界面能带结构调控能力的问题，使研制高灵敏度、低功耗、集成化的布尔逻辑器件面临挑战。本项目拟采用化学气相沉积法制备最优掺杂浓度的p-ZnO:Sb/n-ZnO纳米线，其具有较低载流子浓度的电荷耗尽区和匹配的晶格，为解决压电势屏蔽和界面缺陷问题提供了新的物质载体。构筑p-n结型LSGT器件，并集成高性能的半加器、半减器、全加器和全减器等布尔逻辑器件。通过p-n结减弱压电势屏蔽效应并降低器件能耗，增强压电势调制器件电输运性能的能力，从而显著增强器件的压敏和光敏性能。本项目的顺利实施对ZnO基布尔逻辑器件的材料制备、电学输运和压电势屏蔽效应研究奠定理论和实验基础。

ZnO纳米线应变门控晶体管集成的布尔逻辑器件在可穿戴电子设备领域具有广阔的应用前景。然而，本征ZnO纳米线内部过高的自由电子浓度导致压电势屏蔽效应和高能耗的问题减弱了压电势对界面能带结构调控能力的问题，使研制高灵敏度、低功耗、集成化的布尔逻辑器件面临挑战。本项目采用了化学气相沉积法制备了Fe 掺杂的ZnO纳米线。X射线光电子能谱对ZnO:Fe纳米线测试结果表明Fe成功掺入ZnO，形成了受主缺陷。对纳米结构p-ZnO:Fe样品进行室温PL谱测试显示Fe掺入ZnO后形成了稳定的浅受主能级FeZn-VZn。4.65 K的低温PL谱测试，结果显示本征ZnO的 PL谱中只有近带边发射峰，它是由施主束缚激子(D0X)引起；而ZnO:Fe样品PL谱的主要发射峰是3.362 eV的受主束缚激子（A0X）发射峰。除此之外，Fe掺杂后还在ZnO中引入了受主能级跃迁（FA）的发射峰和施主-受主电子对（DAP）复合峰。这些发射峰的存在证明了Fe成功掺入ZnO，且在ZnO价带顶部引入了浅受主能级。Fe元素掺入ZnO后，电子、空穴分别集中在p型ZnO外、内表面，空穴在内表面形成一个局域电荷储存层。因此，ZnO晶体电荷传输是从内表面传输到外表面，大大缩短了传输距离.基于此p-ZnO纳米线制备了成紫外光电探测器，表明Fe元素的p型掺杂能够使器件的响应时间大幅度缩短，有利于提升其压电光电子学效应。我们构筑了基于p-ZnO:Fe纳米线的应力门控晶体管，并集成了高性能的反相器、与非门、或非门和异或门等布尔逻辑器件。通过p型掺杂减弱压电势屏蔽效应并降低器件能耗，增强压电势调制器件电输运性能的能力，从而显著增强器件的压敏性能。本项目的顺利实施对ZnO基布尔逻辑器件的材料制备、电学输运和压电势屏蔽效应研究奠定理论和实验基础。