基于多电压的三维集成电路布局规划研究

Three dimensional integrated circuits (3D-ICs) are realized by stacking several chips/dies vertically based on through-silicon vias (TSVs). The reduced wirelength can improve both the integration density and the performance. Therefore, it is considered to be most promising for advanced ICs development. However, the stacked chips/dies will cause higher power density compared to 2D-ICs. The resulted local heating effect is acknowledged as the most critical challenges for the reliability and applicability of 3D-ICs. The multiple-supply-voltages (MSVs) based low power design technique is one of the effective methods to solve this problem. Regarding the design challenges faced by MSV-based 3D-ICs floorplanning, our research will focus on following parts. Firstly, by modeling the thermal effect and physical architecture of 3D-ICs, the voltage assignment and its co-optimization with flooplanning algorithm will be proposed. Secondly, by exploring the deadspace management method during floorplaning, we develop the level shifter planning algorithm under both the timing and physical constraints. Thirdly, by power/ground (P/G) network modeling, a voltage drop driven power pad assignment and P/G TSV placement algorithm will be proposed. Finally, experimental verification platform is established to verify the validity of the proposed methods. The project will provide scientific guidance and technical support for 3D-ICs design, which has important theoretical value and application prospect.

三维集成电路(3D-ICs)通过硅通孔(TSV)实现芯片层垂直方向上的堆叠，缩短了互连线长度、提升了芯片的集成度和性能，成为未来集成电路的重点发展方向。但芯片堆叠会使得功率密度大幅增加，带来的局部热效应是影响3D-ICs可靠性和应用所面临的最大难题。基于多电压的低功耗技术是解决这一难题的有效途径之一。针对多电压3D-ICs在布局规划阶段面临的设计挑战，本项目的主要研究内容如下：针对3D-ICs物理结构和热效应进行建模，提出多电压分配算法并结合布局规划实现协同优化算法；研究布局规划过程中的空白面积管理方法，发展时序和物理约束下的电平移位器规划算法；研究3D-ICs的电源/地(P/G)供电网络模型，提出电压降驱动的多电压3D-ICs供电引脚配置和P/G TSV布局方法；建立实验验证平台验证所提出方法的有效性。课题的开展将会为3D-ICs设计提供科学指导和技术支撑，具有重要的理论价值和应用前景。

基于多电压的低功耗技术能有效缓解集成电路热效应，但其带来的设计复杂性给自动化设计工具带来新的挑战，本项目从物理级布局规划和逻辑级综合优化两个方面开展研究。在物理级，1) 研究了多电压布局规划中的快速收敛算法，通过插入虚拟电平移位器，提出启发式多电压分配算法等，提出的方法能优化功耗达12%，加速CPU时间48%，而仅耗费4%面积；2) 研究了多供电引脚配置算法实验结果与普通芯片的供电引脚配置算法相比，我们能优化电压降达 16.9%，时间能加速达4倍之多。在逻辑级，3) 采用基于多数逻辑的进位链综合方法，将通用计算中非算术单元部门进行加速，结果表明对于非算术逻辑电路，提出的方法能够继续优化映射性能达8%；4) 开展了基于多数逻辑门的函数分解算法。 布尔函数分解是用若干子函数的组合来表达一个较复杂的布尔函数。对应逻辑电路设计，设计目标是用较小的成本完成相应的逻辑功能，其中设计成本考虑的是面积(结点数目)，速度(逻辑深度)，功耗(开关活动性)等，我们研究了布尔函数采用多数逻辑运算符分解的条件及算法实现，结果表明该方法应用于逻辑综合流程中能优化平均9.6%的查找表(LUT)的数目和逻辑深度乘积。5) 最后，针对存在缺陷 CMOL 电路的单元容错映射问题 ，提出了一种分级选择电路门节点的容错映射方法，实验结果表明, 与已有算法相比, 该方法平均选择配置的门节点总数明显减少, 在纳米二极管常开缺陷密度为40%、牺牲0.18%线长的情况下, CPU平均运行时间减少了30.68%。