高性能双栅高k介质MoS2场效应晶体管的介质屏蔽效应及界面工程

The project aims at high-performance few-layer MoS2 (FL-MoS2) field-effect transistor (FET) with dual-gate high-k dielectrics. A new stacked gate structure of (HfTiO/Al2O3)/FL-MoS2/HfSiO/Si is proposed and prepared, where fabrication technologies of the high-k top/bottom gate dielectrics by ALD, the high-k/MoS2 interface properties and high-k dielectric screening effect are key research contents. Through using high-k stacked HfTiO/Al2O3 and HfSiO as top- and bottom-gate dielectric respectively to form encapsulation on MoS2 channel, not only can the good Al2O3/MoS2/HfSiO interfaces be obtained, but also the screening effect of high-k dielectric on charged-impurity scattering can largely be enhanced, effectively reducing Coulomb scattering and largely boosting mobility of carriers, and simultaneously decreasing equivalent oxide thickness of the top- and bottom-gate dielectrics and enhancing their gate-controlling ability, thus comprehensively improving performances of the transistor, e.g. the on-current, current on/off ratio, transconductance, subthreshold slope and short-channel effects and so on. Also, the optimal technologies and conditions of fabricating the above high-k gate dielectrics by ALD will be investigated, and the prototype sample of the relevant dual-gate high-k dielectric FL-MoS2 FETs is prepared. It is expected that the encapsulation of the high-k top/bottom gate dielectric can scale down channel length of the MoS2 transistor to below 10 nm, still maintaining excellent electrical properties.

以高性能双栅高k介质几层MoS2(FL-MoS2)场效应晶体管为研究目标，设计制备新型(HfTiO/Al2O3)/FL-MoS2/HfSiO/Si栅堆栈结构，重点研究ALD高k顶/底栅介质及其与MoS2的界面特性以及屏蔽效应。通过采用HfTiO/Al2O3堆栈和HfSiO高k介质分别作为顶/底栅介质，对MoS2沟道形成良好包封，不仅能获得好的Al2O3/MoS2/HfSiO界面特性，而且能大大增强高k介质对荷电杂质散射的屏蔽效应，有效减小库伦散射，提高迁移率，同时减小顶/底栅介质等效氧化物厚度，增强栅控能力，使晶体管的通态电流、通/断电流比、跨导、亚阈斜率以及短沟道效应等得到全面改进。将研究ALD制备上述高k栅介质的最佳工艺和条件，研制出相应的双栅高k介质FL-MoS2场效应晶体管原型样品。由于高k顶/底栅介质的包封使用，有望使MoS2晶体管沟长缩短至亚10nm而仍具有优良的电性能。

MoS2以其合适的禁带宽度、原子级厚度、可免除短沟效应等有望成为下一代CMOS器件的沟道材料。因此，本项目开展相关研究具有重要科学意义和应用前景。.本项目围绕栅介质与MoS2的界面工程以及栅介质材料、结构和制备工艺等开展了深入研究，取得许多重要成果：①构造了云母作为栅介质的顶栅MoS2晶体管，获得了极佳电性能：开关比达到108，迁移率提高到134cm2/Vs，亚阈值摆幅SS减小到72mV/dec，通态电流Ion接近60A/m；②以云母作为绝缘台面暨栅介质，通过干法转移MoS2薄片至其上，制备出8.7nm的垂直短沟道MoS2晶体管，获得低的SS(73mV/dec)和高的Ion (>100A/m)；③采用ALD交替淀积HfO2和Al2O3制备了Hf1-xAlxO栅介质，利用Al掺杂改善界面特性，在Al含量为50%时获得最佳器件性能: 为49cm2/Vs，SS为129mV/dec，开/关比为3.8107；④采用高/低温两步淀积法制备高k顶栅介质，获得栅介质的高质量生长及优良电性能，达到83.3cm2/Vs, SS为83mV/dec,界面态密度Dit低至11012eV-1cm-2；⑤比较分析了不同等离子体处理栅介质对晶体管性能的影响，发现NH3等离子体处理效果最佳，以处理的HfO2为栅介质制备了顶栅MoS2 FET，获得1.6107的开关比，87cm2/Vs的，72 mV/dec的SS；⑥以Al2O3/HfO2堆栈介质包覆MoS2沟道分别制备了顶栅和背栅MoS2晶体管，比较发现顶栅晶体管性能更优：开关比达108，达到102cm2/Vs，SS为93mV/dec；⑦ 采用CVD法在Al2O3表面淀积MoS2薄膜，对比研究了酸处理和未处理Al2O3对MoS2薄膜生长的影响。结果显示，前者生长的MoS2薄膜尺寸增大，性能增强，所制备的晶体管呈现出比未处理样品更好的电特性。