低介电常数、低杨氏模量介质材料在三维垂直互连中的应用探索

The proposal investigates the application of low-dielectric, low-Young's Moudulus materials in through-silicon-via (TSV) technology to realize low-capacitance, high-reliablity TSV for application in interposer. By replacing the conventional SiO2 insulation with the low-k liner as the surrounding insulation between Cu-core and Si-substrate, the capacitance of TSV can be effectively reduced, leading to significantly improvement in electrical performance. Additionally, due to the low-Young's Modulus, the liner can be acted as stress buffer between the Cu-core and Si-substrate to decrease the thermal stress, resulting in high reliability. .To develop the low-capacitance,high-reliability TSV technique, this proposal will carry out investigation on modeling, fabrication and test. Firstly, the electrical performance and thermal-mechanical reliability will be simulated to achieve the design guide rules for proposed TSV technique. Secondly, the key fabrication techniques will be systematically investigaed by experiments to develop resonable integration processes. Then, the electrical and thermal characterizations of the proposed TSV will be tested and further improved approach will be discussed.

本项目尝试探索低介电常数、低杨氏模量介质材料在三维垂直互连中的应用，旨在实现低电容、高可靠性的三维垂直互连结构，并在硅插入层（interposer）中使用。通过采用低介电常数介质材料代替传统的SiO2绝缘层，作为垂直铜导体与硅衬底之间的隔离，能够有效降低三维垂直互连的寄生电容，改善电学性能；同时，该介质材料具有低杨氏模量，可以作为铜导体与硅衬底之间的缓冲层，改善热应力问题，提高三维垂直互连的可靠性。.本项目的研究内容主要分为三部分，从理论计算、关键技术、以及测试验证三个方面展开，旨在获得设计指导方法，攻克关键技术，并且探索优化方案。第一部分是电学性能和热力学可靠性的理论计算研究；第二部分通过系统地开展实验，攻克关键技术，获得可行的制造方法；第三部分是测试验证，同样包括电学和热力学两部分。

为适应低寄生电容、高热-机械可靠性硅通孔发展需求，通过将传统旋涂工艺与真空处理相结合，提出一种适应小直径高深宽比硅通孔侧壁绝缘介质层沉积新工艺，即“真空辅助旋涂”技术，实现了低介电常数、低杨氏模量介质材料在三维垂直互连中的应用探索。.本项目的研究内容主要分为三部分，从理论计算、关键技术、以及测试验证三个方面展开，旨在获得设计指导方法，攻克关键技术，并且探索优化方案。第一部分是电学性能和热力学可靠性的理论计算研究；第二部分通过系统地开展实验，攻克关键技术，获得可行的制造方法；第三部分是测试验证，同样包括电学和热力学两部分。