基于自适应双向时钟拉伸的VLSI时序余量片上消除方法及其电路实现

PVT variations are becoming more serious for VLSI circuits under nanometer process, which makes the traditional VLSI design need to preserve a large timing margin in case of the worst case. Since the actual variations are unpredictable during run-time, it results in power and performance waste. This problem becomes severe in the near threshold voltage (NTV). Two main kinds of timing monitoring techniques can eliminate the timing margin, while they have their own pros and cons. The error prediction technique has a low cost but is unable to eliminate the entire timing guard band. While the error detection technique can eliminate the timing margin entirely, it needs extra error recovery mechanism, and it has a serious throughput loss during the error recovery time. This project aims to explore a novel method which can eliminate the timing margin totally while without generating real timing errors. The key point is to propose an adaptive bi-directional clocking circuit for very fast frequency adjustment within-a-cycle, and to replace the registers at the end of critical paths with the data transition detectors and latches. In this way, when there is a timing violation, the late-arrived data can still be transferred to output correctly, and at the same time, the clock cycle is stretched immediately to avoid further timing failure. Plus, the frequency can be increased as well when the timing is not critical for a long time. The proposed holo-symmetrical transition detector can operate correctly at Near-threshold with a low cost, making this technique appropriate for the low voltage. The proposed technique eliminates the on-chip timing margin at a low cost without error recovery mechanism, which allows the circuit to operate at a practically highest energy efficiency point, which is very meaningful.

纳米工艺下芯片性能受PVT偏差影响加大，使传统IC设计方法需为最坏情况预留较大的时序余量，而芯片运行时处于何种偏差难以预测，导致了功耗和性能的浪费，此问题在低电压下更加严峻。目前两大类能在片上消除/降低时序余量的方法各有利弊：预测型监测技术实施代价小，但仍需保留一定的余量；出错改错型能完全消除余量，但需要额外的改错机制，且吞吐率损失严重。本项目拟突破上述两难困境，奥妙在于，提出一种能当周期立刻响应的自适应时钟双向拉伸电路，将电路关键路径末端的触发器替换为数据跳变检测器和锁存器，则可在时序违规时用锁存器正确传输数据，同时立即拉伸时钟使时序不出错；还能在长时间时序宽松时升高频率以提高性能。此外，提出的全对称结构的数据跳变监测单元可在近阈值下稳定工作、面积代价小。本方法适用于宽电压，以无需改错的低代价，获得了芯片运行时完全消除时序余量的效果，可使芯片工作在实际可行的最高能效，具有重要意义。

先进工艺下PVT偏差对电路性能和功耗的影响巨大，目前两大类能在片上消除/降低时序余量的方法各有利弊：预测型监测技术实施代价小，但仍需保留一定的余量；出错改错型能完全消除余量，但需要额外的改错机制，且吞吐率损失严重。本项目突破了上述两难困境，提出基于自适应双向时钟拉伸的VLSI时序余量片上消除方法，并进行了电路实现和流片验证。首先从理论上分析PVT偏差影响下如何进行监测单元及上层电压频率调节设计，方可在无需改错的前提下实现时序余量的完全消除。其次，提出并设计了能当周期立刻响应的自适应时钟拉伸电路，再次，设计了新型数据跳变监测单元，可在近阈值下稳定的监测晚到的数据，且面积代价小。最后，针对在线监测技术中短路径修复复杂、代价大的难题，提出了基于时钟控制传输门的短路径填充方法，有效降低修复代价，同时提高监测系统的可靠性。以上四个关键技术应用到若干电路中，将电路关键路径末端的触发器替换为数据跳变检测器和锁存器，可在时序违规时用锁存器正确传输数据，同时立即启动自适应时钟电路来拉伸时钟周期，使时序不出错；还能在长时间时序宽松时升高频率以提高性能。本方法以无需改错的低代价，在芯片运行时完全消除时序余量。