近阈值超宽电压电路的PVT偏差弹性设计方法研究

Due to the variable workload of high performance SoC chip, it has the contradictory need of both performance and energy efficiency, thus ultra wide range voltage circuit which covers near/sub threshold voltage to normal voltage becomes the right solution. The highest energy efficiency of SoC circuit mostly exists in near threshold voltage area, however, the potential of near-threshold circuit cannot be released if the severe PVT variations due to advanced process and low voltage are not solved. In this project, based on the previous research on low power adaptive voltage scaling, we aim at exploring an effective PVT variation resilient design methodology for ultra wide range voltage circuit, which will adaptively tune the working frequency and supply voltage through on-chip monitoring the circuit timing effect due to PVT variations, in order to sufficiently release the design margin to improve the energy efficiency. Firstly, the PVT variation mechanism in near-threshold voltage is studied, and gate delay and path delay distribution model are built; then aiming at two problems in NTV resilient design, a new timing monitor circuit with adaptive monitor window and its tuning system is proposed, as well as a new method to guide the critical paths monitoring selection based on critical path delay statistical method considering path activation rate. The above methods propose new solutions for ultra wide range voltage circuit to make it be able to adapt to the practical PVT variation, and thus is very valuable for real applications.

高性能SoC芯片应用负载多变，面临性能和能效的矛盾需求，工作电压覆盖近/亚阈值至常压区的超宽电压电路是解决之道。SoC最高能效通常位于近阈值，但若不解决先进工艺及低电压带来的严重PVT偏差影响，就无法发挥其能效潜力。拟在前期研究低功耗自适应电压调节的基础上，探索一套在超宽电压范围内有效适应PVT偏差的弹性设计方法，通过在线实时监测偏差对时序的影响，据此自适应调节电路工作频率和电压，从而充分释放设计余量、提高能效。首先研究近阈值PVT偏差机理，建立门电路和路径延时分布模型；然后针对弹性设计在近阈值超宽电压下的两大难题，提出监测窗口自适应调节的监测单元及调节系统，以及一种考虑激活率的路径延时统计分析新方法来指导关键路径监测点的选取，降低实现代价；最后构建SoC验证平台验证有效性。以上方法为近阈值超宽电压电路提出了新的解决方案，使芯片能充分适应实际的PVT偏差情况，具有重要的实际应价值。

面对负载多变的SoC系统芯片面临的性能和能效的矛盾需求，工作电压覆盖近/亚阈值区至常规电压区的超宽电压电路是解决之道，其中SoC最高能效工作点通常位于近阈值区，但近阈值区的性能低且PVT（工艺、电压和温度）偏差严重。本项目致力于解决低至近阈值区的超宽电压SoC电路存在的PVT偏差对电路性能和功耗的影响，提出了一套在超宽电压范围内有效适应PVT偏差的弹性设计方法。通过在芯片内部关键路径上插入时序监测单元，实时监测PVT变化对电路性能的影响，结合自适应电压频率调节来尽可能地降低设计时预留的余量，达到了提高性能或降低功耗的效果，从而充分释放设计余量、提高能效。首先研究了近阈值PVT偏差机理，建立门电路和路径延时分布模型，以此指导宽电压下监测单元的监测窗口设置以及监测路径的优化选取。其次，针对普通监测单元难以覆盖住低电压下延时的严峻偏差的问题，设计了低电压下也能稳定工作且代价低的新型监测单元，并提出监测窗口自适应调节技术，能在保证功能正确的前提下使弹性设计具有较高的收益。接下来，针对低电压下关键路径延时的波动更严重造成的监测路径数量过多的难题，提出了考虑激活率的最优化关键路径监测点选择方法，在保证监测到可能造成时序违规的关键路径的同时尽可能地降低需要插入的监测单元数量，降低了实现代价。最后构建了SoC验证平台，经过若干次40nm和28nm CMOS工艺流片，有效验证了以上方法的效果。项目累计发表论文20篇（其中一作/通信作者SCI论文15篇，包含顶级期刊IEEE JSSC 3篇、TCASI 2篇等）、授权/受理第一发明人的发明专利19项（包含美国专利3项）。本项目的实施为近阈值超宽电压电路设计提出了新的解决方案，使芯片能充分适应实际的PVT偏差情况，具有重要的实际应用价值。