一种运用键合技术的全新3D集成封装方法核心工艺的研究

In order to keep up with the needs of the astonishing development in the functionality of portable devices and of computational systems, integration technology has been investigated over the past three decades. Further requirements on form factor reduction, performance improvement, and heterogeneous integration will make three-dimensional integration a plausible choice as the next generation of microsystem manufacturing technology, as it can provide an excellent connection density higher than 10e4/mm2 for developing "More than Moore" scaling. In recent years, bonding technology has become a very important packaging and integration technology for the realization of three-dimensional integrated circuits (3DICs). The 3D integration can be achieved by a combination of bonding and through-silicon via (TSV). However the complicated fabrication process and high cost are defined as the bottlenecks in industry application. This subject intends to propose an innovative low-cost and simple technical process for 3D integration and packaging. The research work will concentrate on developping and optimizing the new integration (or packaging) technology. The Cu damascene process will be used as the interconnection technology in 3D integration/packaging. The contact resistances are estimated on the oder of 10^(-3)Ohm. In consideration of new characterics and new requirements of integrated or packaged devices, this subject will focus on the surface treatment before Cu-to-Cu diffusion bonding. Another target of this subject is to design and fabricate the microelectromechanical systems (MEMS) accelerometer for gravitational experiment. The final objective of this subject is to encapsulate the micro-device in a Si cap using metal diffusion bonding.The hermeticity must be smaller than reject limit (5e10-8atm.cm^3/s) described by the MIL-STD-883E standard. The results of this research on bonding technology is very attractive in 3D integration for packaging of devices in large-scale integration technology, not only in theory but also in application.

随着移动通讯和高性能计算机的发展，现有的2D集成技术已经严重制约了器件微型化以及系统运行速度的提升。而3D集成封装技术在微型化方面拥有巨大的优势，并且3D集成技术使得器件之间的连线将变得更短，系统的运算速度也将得到前所未有的提升，同时能耗与延时也将大大地降低。近年来，键合技术作为一种行之有效的方法，在3D集成封装领域得到了前所未有的关注。虽然现阶段键合技术结合硅通孔技术作为实现芯片之间互联的最新技术，正在3D集成封装技术中被广泛的研究，但其高昂的价格以及其复杂的制造工艺也制约它被大规模应用。本课题将提出一种低成本的3D集成封装设计，此设计拟采用铜铜扩散键合为主要集成封装技术把微电子器件封装其中，控制封装后的漏气率小于5e10-8atm.cm^3/s。封装中运用大马士革工艺实现芯片之间互联技术，每个结点的阻值控制在毫欧量级。由于整个工艺中未涉及硅通道技术，因此这种工艺的造价将相对低廉。

相比传统加速度计，硅基加速度计具有较好的品质因数，较低的热噪声水平，及较高的测量精度。封装在微电子工业中有着迫切的需求以及广泛的应用前景，它不但能够使相关器件工作于良好的环境，对其精确度的提高以及性能的稳定性与可靠性的提升也有着巨大的帮助。为了深入研究键合工艺在封装中的应用，本项目开展了针对铜铜扩散键合的研究，首先对通表面处理技术做了较为详细的探讨，利用不同的方法防止表面氧化为后期工艺带来的影响。其次，利用一种新型的光敏材料充当绝缘层，完成了不同金属层之间的跨连工艺。最后利用我们的研究成果成功研制出了大动态范围高分辨率的MEMS加速度计，在1Hz处的噪声由于30ng/√Hz，量程大于1g，封装气密性优于美军标要求。