单体三维碳纳米晶体管存储器的容错技术研究与实现

Monolithic 3D Integrated (M3I) memories are promising for energy-efficient computing in big-data and machine-learning applications. Due to the temperature constraint of M3I during the fabrication process and the run time, CMOS technology is impossible for fabricating M3I chips. Carbon Nanotube FET (CNFET) has extreme low power; its energy-efficiency is an order of magnitude better than CMOS FETs, which makes CNFET-SRAM a natural choice for M3I memory. However, CNFET has severe process variation with special spatial correlations, rending the successive and correlated faults in CNFET-SRAMs. The whole M3I memory chip has to be discarded if any layer contains an irreparable fault; the pre-bond test, a possible solution widely used in stacked 3D IC (3D-SIC), is not applicable to M3I. It results in a degraded yield for M3I CNFET-SRAM. To solve this problem, in this project, we propose several novel approaches: 1) we establish a 3D fault model based on the characterization of CNT growth, using image-processing, curve-fitting and statistical methods; 2) we prove that the “Mid-growth test” can reduce the overall cost significantly by studying the design for test (DfT) method for “incomplete” M3I CNFET-SRAM cell structure and exploring the “3D Jump Test” method, leveraging the spatial correlation of M3I CNFET-SRAM; 3) based on the 3D fault model, we explore a novel repair architecture to share the redundant resources within a die and across different dies, taking the advantage of the high vertical bandwidth in M3I; 4) we build an open-source cost evaluation tool for M3I CNFET-SRAM to reveal the complex relationship among various design parameters, including the choice of CNFET processes, the number of M3I layers, the design of M3I CNFET-SRAM cell, the choice of test algorithms, the redundancies sharing schemes and repair algorithms. We can also use the cost evaluation tool to verify the feasibility of “Mid-growth test” and redundancy sharing schemes. The success of this project can enhance the yield of M3I CNFET-SRAM and reduce their manufacture cost, which serves as the first step for the mainstream adoption of this emerging integration paradigm. The results can be used as a reference of inventing test and fault tolerance methods for other emerging memories.

单体三维存储器效能极高，适用于大数据和机器学习等应用；但其制造过程有严格的温度限制，很难用传统CMOS晶体管制造。碳纳米晶体管的能效要比CMOS晶体管高一个数量级且功耗极低，是实现单体三维存储器的理想器件；但碳纳米管生长时有特殊的工艺波动，碳纳米晶体管故障率高。针对这一问题，本项目用图形图像处理技术和统计学方法，研究基于碳纳米管形态特征的故障建模方法；通过对“不完整”存储单元的可测试性设计和对“三维跳跃式测试”方法的研究，揭示“生长中测试”有效降低制造成本的规律；根据独特的故障分布，探索单层存储器的冗余共享机制，进一步利用单体三维芯片的高带宽优势，探索“多层冗余共享”机制和修复算法；建立开源成本评估工具，明确器件层的工艺选择、电路层的存储单元设计，架构层的测试与修复机制之间的互相关系。项目预期能提高该新型存储器的良品率，为其产业化提供方案，为其它新工艺存储器的容错技术研究提供参考。

单体三维存储器效能极高，适用于大数据和机器学习等应用;但其制造过程有严格的温度限制，很难用传统CMOS晶体管制造。碳纳米晶体管的能效要比CMOS晶体管高一个数量 级且功耗极低，是实现单体三维存储器的理想器件;但碳纳米管生长时有特殊的工艺波动 ，碳纳米晶体管故障率高。针对这一问题，本项目用图形图像处理技术和统计学方法，研 究基于碳纳米管形态特征的故障建模方法;通过对“不完整”存储单元的可测试性设计和 对“三维跳跃式测试”方法的研究，揭示“生长中测试”有效降低制造成本的规律;根据 独特的故障分布，探索单层存储器的冗余共享机制，进一步利用单体三维芯片的高带宽优 势，探索“多层冗余共享”机制和修复算法;建立开源成本评估工具，明确器件层的工艺 选择、电路层的存储单元设计，架构层的测试与修复机制之间的互相关系。项目预期能提 高该新型存储器的良品率，为其产业化提供方案，为其它新工艺存储器的容错技术研究提供参考。