深度学习高性能硬件加速架构研究与设计

Deep learning is a major breakthrough in the field of artificial intelligence. For image recognition, video recognition and analysis, voice recognition and so on, deep learning has achieved great success. However, major deep learning algorithms rely on deep neural network, which leads to significant computational and memory complexity. Hence, the deployment of deep learning algorithms in various power limited embedded platform is quite challenging. This proposed research project focus on efficient VLSI architectures for deep learning algorithms. The target of this project is developing high performance, low power hardware architectures for deep learning. In more details, this project will first explore various model reduction schemes, such as computational complexity reduction, network parameters reduction and so on. In the next, the corresponding low power high performance hardware architectures will be designed and implemented with FPGA.

深度学习是人工智能领域的重要突破。在图像识别，视频识别与分析，语音识别等领域，深度学习取得了巨大的成功。但是，主流的深度学习算法依赖于深度神经网络，这导致了较大的计算和存储复杂度。这使得在功耗受限的嵌入式平台上部署深度学习算法变得非常具有挑战性。本研究项目聚焦深度学习算法的硬件加速架构，研究并设计高性能、低功耗的深度学习算法加速单元。具体而言，本项目主要关注深度学习中使用的深度卷积神经网络和深度递归神经网络，探索降低算法计算复杂度、神经网络参数数目等降低模型复杂度的方案。基于对网络的简化方案的研究，本项目将设计对应的低功耗、高性能硬件架构并用FPGA实现。

深度学习是人工智能领域的重要突破。在图像识别，视频识别与分析，语音识别等领域，深度学习取得了巨大的成功。但是，主流的深度学习算法依赖于计算量和参数量巨大的深度神经网络，相较于传统算法能显著提升各项任务精度指标的同时，也使其在功耗受限的嵌入式平台上的部署变得非常具有挑战性。本研究项目聚焦深度学习算法的硬件加速架构，研究并设计高性能、低功耗的深度学习算法加速单元。具体而言，本项目主要关注深度学习中常用的深度卷积神经网络和深度递归神经网络，探索降低算法计算复杂度和神经网络参数数目等减小模型复杂度的各种方案。基于对算法复杂度深度简化的研究，本项目设计了对应的低功耗、高性能、专用或可重构硬件架构，并用FPGA实现和验证。