栅介质/Si1-xGex(x≥0.5)界面特性的理解与调控研究

Since IBM delivered its working samples of chips with seven-nanometer silicon-germanium based transistors in July 2015, Si1-xGex(x≥0.5) attracts much more commercial attention as potential CMOS channel material. Interfacial control between dielectrics and Si1-xGex(x≥0.5) is crucial for the device performance, while the direct-relevant research is still insufficient. Based on our past experience of dielectrics/Ge interface study, this project focuses on the interfacial control of dielectrics/Si1-xGex(x≥0.5) including surface roughness and interfacial defects. Atomically flat Si1-xGex(x≥0.5) surface with step and terrace structure is proposed to be prepared by H2 annealing/Wet chemical cleaning approaches via optimizing the controlling factor, to reduce the carrier scattering during the devices operation. Also, an ultrathin multi-element film composed of binary/ternary oxide is proposed to be inserted between dielectrics and Si1-xGex(x≥0.5) as passivation layer via a co-sputtering method, to further improve interfacial quality with the passivation effect to the interfacial defects. We will also investigate the electronic structure of dielectrics/Si1-xGex(x≥0.5) by using x-ray photoemission spectroscopy and internal photoemission spectroscopy, to understand the connection between process control, interfacial defects, electronic structure and the device performance. The insight into the mechanism of interfacial defects on device performance is expected to be revealed. This study will provide both theoretical and technical support on the fabrication process control of high performance seven-nanometer silicon-germanium based transistors.

Si1-xGex是具有巨大商业化应用前景的CMOS器件沟道材料， 2015年7月IBM发布了首款7nm Si1-xGex原型芯片。良好的栅介质/Si1-xGex界面是提升器件性能的关键。在前期栅介质/Ge界面研究基础上，本项目针对栅介质/Si1-xGex(x≥0.5)界面，从界面粗糙度及界面缺陷控制出发，拟优化氢气退火处理/湿化学表面清洗工艺，制备原子级平坦Si1-xGex(x≥0.5)表面，并利用多靶磁控共溅射制备多元氧化物作为极薄钝化层钝化栅介质(如HfO2)/Si1-xGex(x≥0.5)界面缺陷，降低界面粗糙度及缺陷引起的载流子散射，提升器件性能。同时，开展x射线/内光电子能谱界面电子结构研究，建立工艺参数、界面缺陷、电子结构及器件性能之间联系，阐明界面特性影响器件性能的内在物理机制。本课题的实施，将为制备7nm及以下的Si1-xGex(x≥0.5)高性能器件提供理论与技术支持。

锗是集成电路产业先进技术节点用取代硅基CMOS器件的关键半导体沟道材料。本项目以以锗沟道材料为主要研究对象，围绕栅介质筛选、高质量栅介质/Ge界面优化、界面电子结构解析、高性能晶体管器件制备、锗/新型TMDs薄膜杂化沟道器件构筑等开展了系统研究。通过本项目的实施，我们(1)成功筛选出YOx作为与Ge衬底具有良好相容性的栅介质，确定了高质量栅介质/Ge堆栈结构最佳工艺条件，制备了高性能柔性Ge纳米线场效应晶体管器件，器件具有高的载流子迁移率~17 cm2V−1s−1，开关电流比~2×103，阈值电压~-0.36V及良好的稳定性和柔性；(2)解析了GeO2/Ge堆叠结构界面电子结构，阐明了缺陷影响Ge基CMOS器件性能影响机理，为理解栅介质/锗界面特性提供了新的思路；(3)开发了大范围MoTe2纳米带阵列的CVD相可控制备及转移工艺，实现了Ge/MoTe2异质结光电探测器器件构筑及性能研究。此外，本项目还拓展研究了集成电路先进技术节点用新型MoTe2、WTe2薄膜相可控合成、表面氧化动力学特性、铁磁性掺杂、电化学特性等。课题的顺利执行为集成电路先进技术节点用取代硅CMOS工艺提供了一定的理论与技术支持。项目执行期间，共发表期刊论文12篇，会议论文3篇，英文学术书籍章节一章；项目负责人获批湖北省楚天学者计划（楚天学子），华中科技大学华中卓越学者晨星岗；培养研究生11名。