三维集成电路的TSV建模和信号完整性关键技术研究

The project will study the key underlying scientific issues of TSV analytical model, TSV electromagnetic model, interconnect signal integrity based on the copper and carbon nanotube bundles TSV. Based on the copper TSV and the carbon nanotube bundles TSV technology, considering the length, diameter, dielectric thickness and spacing of the TSV factors, to create a three dimensional integrated circuit the TSV through-holes resistor, inductor, capacitor analytical model study TSV structures parameters and material. the impact of the electromagnetic parameters of the return loss, insertion loss, and to establish a precise the TSV equivalent lumped model and based on TSV isolation lumped model. The study insert redundant TSV and buffer 3D interconnect delay and power consumption of the analytical model and proposed synchronized improve interconnect delay and signal reflection coefficient of the TSV dimensions and layout optimization algorithm. Considering the coupling of the three-dimensional integrated circuits, delay and power consumption constraints, to study the application of multi-level routing techniques to three-dimensional integrated circuits TSV density optimized allocation techniques applied to future integrated circuit design to provide the necessary theoretical and technical foundation for three-dimensional integration technology.

本项目研究三维集成电路铜和碳纳米管束TSV的解析模型、电磁模型、互连信号完整性方面的关键基础科学问题。针对铜TSV和碳纳米管束TSV技术，考虑TSV的长度、直径、介电厚度和间距等因素，建立三维集成电路TSV通孔的电阻、电感、电容的解析模型，研究TSV结构参数和材料参数对其回波损耗、插入损耗等电磁参数的影响，建立精确的TSV等效集总模型和的基于TSV的隔离集总模型。研究插入冗余TSV和缓冲器的三维互连线延时与功耗的解析模型，提出同步改善互连延时与信号反射系数的TSV尺寸与布局优化算法。综合考虑三维集成电路的耦合、延时与功耗的约束，研究应用多级路由技术实现三维集成电路的TSV密度优化分配技术，为三维集成技术应用于未来集成电路设计提供必要的理论和技术基础。

本项目研究三维集成电路铜和碳纳米管束TSV的解析模型、电磁模型、互连信号完整性方面的关键基础科学问题。针对铜TSV和碳纳米管束TSV技术，考虑TSV的长度、直径、介电厚度和间距等因素，建立三维集成电路TSV通孔的电阻、电感、电容的解析模型，研究TSV结构参数和材料参数对其回波损耗、插入损耗等电磁参数的影响，建立精确的TSV等效集总模型和的基于TSV的隔离集总模型。研究插入冗余TSV和缓冲器的三维互连线延时与功耗的解析模型，提出同步改善互连延时与信号反射系数的TSV尺寸与布局优化算法。综合考虑三维集成电路的耦合、延时与功耗的约束，研究应用多级路由技术实现三维集成电路的TSV密度优化分配技术，为三维集成技术应用于未来集成电路设计提供必要的理论和技术基础。