纳米尺度下集成电路版图对单粒子辐射效应的影响机理研究

Soft errors in Integrated Circuits induced by single-event effects severely threaten the safety of spacecrafts. Conventional radiation-hardened techniques, such as adding well contacts, have proven to be effective in mitigating charge sharing. However, this has suppressed good phenomena in advanced nano-scale technology nodes, such as pulse quenching. The proposed project will involve designing inverter chains, DFF and DICE register chains in a 65nm CMOS technology node. By using TCAD simulations and radiation experiments, the mechanisms of how area, distance from sensitive nodes of well contacts, twin/triple well, interspacing between sensitive nodes affect the bipolar gain of parasitic BJTs, charge diffusion, charge collection, and charge sharing will be investigated; how particle LET and supply voltage affect the pulse width of SETs and the critical charge of SEU-tolerant designs will be investigated as well. Eventually the effect of layout on single event errors will be revealed. In addition, the mechanisms of charge sharing in both 65nm and 28nm technology nodes will be compared. After this, the trend of single event errors across nano-scale technology nodes will be revealed. This project will provide experimental results, theoretical foundation for radiation-hardened techniques, forecasting soft error rates, and the development of spaceborne ASIC designs.

处于空间环境的集成电路受单粒子辐射效应引发的错误严重威胁航天器的安全工作。传统加固方法如添加阱接触会抑制电荷共享，但也会削弱纳米工艺下的脉冲窄化等有益现象。为此，面向抑制电荷共享和增强有益效应的需求矛盾，针对版图结构对电荷共享的影响，本项目将利用65纳米CMOS工艺，设计反相器链、DFF和DICE寄存器链，结合仿真和辐照实验，研究阱接触面积、与敏感节点的距离、三阱/双阱工艺、敏感节点之间的距离等版图参数对电荷扩散、收集和共享的作用机制；研究电源电压和粒子LET与单粒子瞬态效应脉冲宽度和翻转效应临界电荷的关系；最终明晰纳米工艺下版图结构对单粒子错误的影响机理。结合前期设计的28纳米芯片，比较两种工艺相同版图结构下的电荷共享机制，进一步揭示单粒子错误与先进纳米尺度缩减的规律关系。为建立新的版图加固理论提供支持，为单粒子错误的预测提供参考，推动航天器集成电路防辐射技术的进一步发展。

纳米集成电路在空间环境中受单粒子辐射效应引发的错误严重威胁航天器的工作。为全面研究版图结构对SEE的影响，并提供基于版图的低开销加固方法，特开展本研究。本项目设计了多种工艺下的测试芯片，通过仿真和实验手段，设计了SEE传感器，可以检测SEE电流影响的N阱电势，适用于时序和组合逻辑电路；通过采集M个阱接触电势值的采集模块、对应N个不同时钟信号CLK的D触发器模块和PISO输出模块组成的传感器，可以实现阱电势在时空上的数值分布测量；研究了公共质心结构应用到数字锁存器中对SEU的影响，通过Quatro（本质上是一个差分锁存器）的传统布局和公共质心布局的结果对比，发现公共质心结构对翻转LET阈值和错误截面的改善很小。提出了适用于SOI工艺的加固触发器设计，与全堆叠晶体管结构相比，仅对Quatro锁存器的2个内部PMOS晶体管进行了堆叠，面积开销较小，仿真和实验结果证明该设计显著提高了翻转LET阈值，并把错误截面降低了3-10倍。提出了适用于体硅工艺的SRAM单元设计，采用12T设计，与传统6T相比具有2倍的面积开销，alpha和质子实验证明了抗SEU性能的提升。对28、65、90和130纳米的同个触发器设计进行LET阈值和错误截面的比较，表明了随着工艺节点的缩减，翻转阈值降低的同时，饱和错误截面也随之降低。