面向下一代移动终端的高性能低功耗主存系统结构

Due to the rapid development of computing capability of mobile devices, "memory wall" has been already become the major bottleneck to the mobile computing platform. In particular, the main memory system of mobile device is also constrained by power consumption, thermal dissipation and physical size. Therefore, it is very challenge to continue to improve the performance of mobile system. The performance and power consumption of main memory has become one of the keys to the success of next generation mobile devices. To meet the requirement of mobile computing system, this project aims to propose the high performance and low power architecture and circuit design of mobile device main memory system. .(1) To propose the low power data retention technique for main memory leveraging the hardware and sofware cross-layer codesign approach; (2) To reduce the power consumption of mobile main memory during active state with the technique of dyanmic voltage and frequency scaling; (3) To exploit the access scheduling methodology for multi-channel mobile main memory system, which is enabled by the 3D integration and wide I/O technology; (4) To propose the architecture design for the DRAM and phase change memory hybrid main memory in mobile devices. The research work in this project is of great importance to both academic research and industrial application.

移动终端计算能力的飞速发展使"存储墙"问题也已成为移动计算平台的主要瓶颈。更为特殊的是，移动终端主存系统还受到功耗、散热和物理尺寸的限制，给系统性能提升带来挑战。有效解决移动终端主存系统的性能和功耗问题成为下一代移动终端成功的关键之一。本课题以移动终端计算系统的需求为背景，结合集成电路工艺与存储器件领域的新进展，研究高性能低功耗的移动终端主存系统的结构与电路设计：采用软硬协同跨层次的研究方法，提出移动终端主存低功耗数据保持技术；利用动态电压与频率调节技术，降低移动终端主存系统激活态功耗；面向三维集成工艺和Wide I/O技术，研究移动终端多通道主存系统的访问控制与调度策略；结合新型非易失性存储器件的进展，提出动态随机存储器和相变存储器混合的移动终端主存系统结构设计。本研究对下一代移动终端主存系统低功耗设计具有重要的研究意义和应用价值。

移动终端计算能力的飞速发展使“存储墙”问题也已成为移动计算平台的主要瓶颈 。更为特殊的是，移动终端主存系统还受到功耗、散热和物理尺寸的限制，给系统性能和可靠性提升带来挑战。有效解决移动终端主存系统的性能、功耗和可靠性问题成为下一代移动终端成功的关键之一。本课题以移动终端计算系统的需求为背景，结合集成电路工艺与存储器件领域的新进展，研究高性能低功耗的移动终端主存系统的结构与电路设计：采用软硬协同跨层次的研究方法，提出移动终端主存低功耗数据保持技术；利用动态电压与频率调节技术，降低移动终端主存系统激活态功耗；面向三维集成工艺和Wide I/O技术，研究三维集成移动终端主存系统的良率与可靠性提升方法；结合新型非易失性存储器件的进展， 提出动态随机存储器和相变存储器混合的移动终端主存系统结构设计，并重点提出非易失性存储器可靠性的信号处理方法。课题研究发表期刊论文6篇，会议论文6篇，申请或获得授权国家发明专利3项。本研究对下一代 移动终端主存系统可靠性和低功耗设计具有重要的研究意义和应用价值。