基于CMOS工艺的10GHz 6bit ADC电路设计及校正方法研究

With the rapid development of broadband application systems, broadband technology increasingly has a high requirement of Flash ADC. At home, great international companies monopolize the low-end market and high-end market is blocked by foreign techniques together with embargo. Therefore, researching self-developed intellectual property in Flash ADC has great using value in practice and significant meaning in academic domain..On the basis of early researches and demand of high performance analog front-end circuits, this project aims at deeper study about 10 GS/s 6bit high performance ADC and is probed into time interleaved technology and merged interpolation and reference voltage. As there is a problem of mismatch between the individual conversion channels, a resolution that statistics-based background timing skew calibration is proposed, combined with relative statistics algorithm and multiple-phase clock of steerable delay to solve the timing skew. Meanwhile, applying high-speed double sample T/H and static comparator with active inductor can satisfy the changing rate of system, which is also a breakthrough to the design of traditional dynamic comparator. Thus, according to all above, there comes a complete plan of Flash ADC, simulation and verification, testing and applying to system, which provides theoretical and technical basis for Flash ADC and enhances the development and applications of the methodology of high performance circuits design.

随着宽带应用系统的快速发展，宽带技术对高速ADC的需求日益迫切。国内低端市场被国际大公司所垄断，高端市场上受到境外的技术封锁并存在禁运的现象，因此，研发具有自主知识产权的高速ADC具有极高的实际应用价值和巨大的学术意义。.基于高性能模拟前端电路的前期科研基础和迫切应用需求，本课题针对10GS/s 6bit 的高性能ADC进行深入研究，探索4通道时间交织技术和单通道高插值和参考电压混合技术。针对多通道ADC的通道间失配现象，重点进行基于统计学的时序倾斜后台校正技术的研究，结合相关函数统计学算法和延时可控的多相位时钟，解决时序相位问题。同时，突破传统动态比较器设计，采用高速的双采样采样保持（T/H）电路和带有有源电感的静态比较器，满足系统转换速率需求。进而建立整套的高速ADC设计、仿真验证、测试验证和系统应用方案，为高速ADC设计提供理论基础和技术支撑，促进高性能电路设计方法学的发展和应用。

基于高性能模拟前端电路的前期科研基础和迫切应用需求，本课题针对10GS/s 6bit的高性能ADC进行深入研究，探索四通道时间交织技术和单通道高插值和参考电压混合技术。针对多通道ADC 的通道间失配现象，重点进行基于统计学的时序倾斜后台校正技术的研究，结合相关函数统计学算法和延时可控的多相位时钟，解决时序相位问题。同时，突破传统动态比较器设计，采用高速的双采样采样保持（T/H）电路和带有有源电感的静态比较器，满足系统转换速率需求。本课题完成了TSMC 90nm CMOS工艺下的四通道时间交织Flash ADC设计与仿真，并实现了两通道结构ADC流片，实现了5GHz、4.02bit有效位的ADC芯片；同时，完成了高速ADC设计方案，在TSMC 0.18um CMOS工艺下，实现了1.25GHz、校正后4.6bit有效位的单通道ADC芯片。本课题建立了针对四通道时间交织与高速单通道结构的ADC设计、仿真验证、测试验证和系统应用方案，为高速ADC设计提供理论基础和技术支撑，促进高性能电路设计方法学的发展和应用。