纳米CMOS集成电路抗老化性设计

CMOS technology scaling significantly pushes the acceleration of circuit aging due to negative bias temperature instability of PMOS transistors, which brings about a serious problem of reliability and lifetime. The existing research work pay their main attention on the techniques to monitor and tolerate circuit aging after it occurs, which are all passive solutions. How to effectively improve circuit actively aging-resistance is an unresolved important problem in the field of integrated circuits reliability. Putting forward an innovative concept of design for aging-resistance (DFA), this project tries to develop the circuit innate aging-resistant ability from the angle of circuit structural aging-resistance design methodology. In this project we will investigate the methods to predicting the early-aging nodes on the critical paths of circuit, including establishing computational aging model and quantitatively representing the degree of aging and collecting aging information by transistor/gate level co-simulation. Circuit aging-resistance design techniques will be investigated in this project, including analyzing the circuit structure aging-resistant characteristics based on combining static and dynamic circuit structure, establishing layered aging-resistant design rules. This project also study topology structure synthesis method considering comprehensive performance norms such as delay, power consumption, area and aging. The research of the project is of important practical significance for a new generation of CMOS integrated circuits to improve its reliability and lifetime and perfect design methodology.

随着CMOS集成电路工艺尺寸的不断缩小，PMOS晶体管的负偏置温度不稳定性（NBTI）引起的电路老化加速，严重影响芯片的可靠性和寿命。现有国内外研究工作主要针对电路老化后的监测与容忍技术，属于被动的解决方案。如何有效实现电路的主动抗老化，是集成电路可靠性领域尚待解决的重要课题。本项目提出电路抗老化性设计（DFA）概念，以电路结构性抗老化技术为切入点，挖掘电路先天抗老化的能力。研究电路关键路径早衰节点的预测方法，包括可计算老化建模与定量表征方法，基于晶体管级/门级联合仿真的老化信息提取方法；研究电路抗老化设计技术，包括静态/动态混合的电路抗老化结构特征分析，建立层次性的抗老化设计规则；将抗老化性约束纳入传统设计流程，应用抗老化设计规则，研究面向时延、功耗、面积和老化复合指标的电路拓扑结构综合方法。本项目研究对提高纳米CMOS集成电路的可靠性和寿命、完善集成电设计方法学，具重要的实际意义。

纳米CMOS集成电路设计与工艺技术快速进步的同时，也使得电路晶体管的偏置温度不稳定性（BTI）引起的电路老化日趋严重，极大地影响了现代集成电路芯片的可靠性和使用寿命。针对国内外已有研究工作的不足，为挖掘电路先天性抗老化的能力，积极探索有效的电路结构层面的抗老化解决方案，本项目以电路结构抗老化性设计技术为目标和切入点，研究了纳米集成电路BTI老化特性建模与分析方法，研究了电路老化关键节点选取及早衰节点预测方法，研究了电路老化信息提取与老化检测方法，重点研究了电路老化缓解与抗老化设计技术，包括基于时序分析与功能仿真的结构性抗老化设计方案和输入向量控制技术，研究了抗老化设计基本规则和老化约束下的电路设计自动化技术与仿真平台。通过项目历时四年的持续研究工作，在相关内容和目标上取得丰富研究成果，发表学术论文70余篇，其中期刊论文60余篇，会议论文13篇，SCI、EI收录论文40余篇，申请专利6项，其中取得专利授权4项，参加国际或国内学术会议超过15人次，邀请或联合邀请同行专家作学术交流报告6人次。直接培养毕业或在读硕士研究生超过16人，参与培养毕业或在读硕士（博士）研究生超过12人。项目研究成果对提高现代纳米CMOS集成电路的寿命与可靠性，对促进集成电路设计方法学的发展，具重要的现实意义。