基于完全自对准结构的单电子晶体管研究

Single Electron Transistor (SET) is one of the nanoelectronic devices which have wider application prospect due to its small volume, low power consumption and higher charge sensitivity. However, there are some problems such as the unsatisfactory gate-controlled property, lower working current, as well as poor controllability in fabrication process and so on, for the SET fabricated by the current technologies. To solve the above mentioned problems, research on the SET based on the self-aligned technology is presented in this project, as well as the fabricated SET is compatible with the CMOS technology. In the project, the main research contents based on the key technologies for SET will be implemented, including the fabrication of the coulomb island, and self-limited oxidition, the design and fabrication of the tunneling barrier, the self-aligned technologies for the gate and coulomb island as well as the coulomb island and source/drain electrode. The key problems will be solved for the controllability of the coulomb island, the structure and film uniformity of the tunneling barrier layer, and the compatibility of the above mentioned two self-aligned technologies. Proceeding to the next stop on the basis of the research contents is the design and fabrication of the SET device. As the key problems to be solved and the special self-aligned technologies to be used in SET, excellent characteristics is expected to be obtained such as good gate-control ability, larger working current and device structure controllability. And then, the related work on the key technologies and the fabricated SET performed in this project will provide a good foundation for the market application in the future.

单电子晶体管具有体积小、功耗低和电荷灵敏度高等优点，被认为是最有应用前景的纳米电子器件之一。然而，目前主流工艺所制备的硅基单电子晶体管存在栅控不理想、工作电流低、制备可控性差等问题。本项目针对以上问题，提出与CMOS工艺兼容的、基于完全自对准技术的单电子晶体管结构研究。主要进行包括10nm以下硅库仑岛制备与硅纳米结构的自限制氧化效应研究、库仑岛表面态密度控制、隧穿势垒层的设计与制备、自对准技术等的研究，重点解决库仑岛的制备可控性、隧穿势垒层的选取以及两种自对准工艺之间的兼容性问题。在此基础上，进行整个器件的研制，以期获得栅控良好、电流量级可测、器件结构可控的完全自对准的单电子晶体管结构。为硅基单电子晶体管真正走上实用化打下良好基础。

单电子晶体管具有体积小、功耗低和电荷灵敏度高等优点，被认为是最有应用前景的纳米电子器件之一。然而，目前主流工艺所制备的硅基单电子晶体管存在栅控不理想、工作电流低、制备可控性差等问题。在本课题中，针对以上问题，提出与CMOS工艺兼容的、基于完全自对准技术的单电子晶体管结构研究。主要进行包括10nm以下硅库仑岛制备与硅纳米结构的自限制氧化效应研究、库仑岛表面态密度控制、隧穿势垒层的设计与制备、自对准技术等的研究，重点解决库仑岛的制备可控性、隧穿势垒层的选取以及两种自对准工艺之间的兼容性问题。经过三年的研究，成功完成了10nm量级的库仑岛制备，表面态密度控制在1012cm-2以下，并且获得了栅控良好、电流量级可测、器件结构可控的完全自对准的单电子晶体管结构。为硅基单电子晶体管真正走上实用化打下良好基础。