碳纳米管电极交叉阵列阻变存储单元构建及开关特性研究

It has been reported by ITRS that the most focused problems to TMO materials for RRAM manufacturing are to achieve high level integration and low power consumption. In this project, we mainly plan to investigate the design and manufacturing technology of novel RRAM devices with low-power and high level integration and nano-memory cell based on comprehensive analysis of RRAM development status. Firstly, horizontal aligned CNTs are deposited on quartz wafer by high temperature CVD process，and they are transferred from quartz to Si wafer by Au and hot melt adhesive film under atmospheric temperature. Carbon nanotubes crossbar electrode arrays are chosen to form the memory cell with nanoscale contact area, whose purposes are to improve the integration of devices cell and reduce the reset current. Secondly, novel RRAM device cells with one switching and one resistor are proposed based on the following experimental results: the VOx cannot maintain low resistance characteristics under lower sweep voltage and ZnO can be used as functional materials, the reset current of which can be adjusted by doping ions. The combining of the above two materials can avoid the overhigh reset current under lower resistance state. In order to resolve the sneak path problem of the novel passive crossbar arrays devices, complementary resistive memories with stacked structure are designed, which will be favorable to achieve high level integration, especially for 3D integration. The switching characteristic consistency will be improved by the well contact interface based on TMO-CMP technology. The CNTs transferring technology effectively overcomes the contradiction between the low temperature 3D integration and high-temperature CNT growth process. Finally, the resistance switching mechanism of novel RRAM with stacked structure will be explored after the analysis of passive RRAM switching characteristics. All the works in this project will provide relevant theoretical guidance for the development of new NVM - passive high density RRAM.

ITRS指出高集成度和低功耗是oxide-RRAM最为关注的问题;本申请在综合分析RRAM的发展现状基础上，着重围绕高集成、低功耗RRAM设计及纳米存储单元的实现开展研究。首先高温生长CNT,通过Au和热熔胶膜实现常温CNT转移;采用碳纳米管交叉电极阵列构建具有纳米接触的存储单元,进而提高集成度,降低reset电流。利用VOx的低电压开关特性与ZnO的可逆阻变特性构建1S1R结构新型RRAM,避免低阻态reset电流较高,并通过ZnO薄膜掺杂进行调控。为解决交叉阵列中潜通路难题,采用叠层互补结构构建无源阵列RRAM,为后续高集成化发展提供可能（3D集成）。结合镶嵌结构通过TMO-CMP改善界面接触特性,提高电学特性一致性;通过CNTs转移技术解决低温3D集成与高温CNT生长的矛盾;优化基础上分析无源RRAM阻变特性,探索叠层结构阻变机制,为新型无源高密度RRAM的研制提供相关基础与理论。

随着集成电路工艺技术节点的不断微细化（32nm向22nm发展），基于电荷存储的Flash非挥发性存储器由于隧穿氧化层厚度越来越小，漏电流变得越来越严重，直接影响Flash存储器的数据保持性能。近几年备受关注的新型阻变存储器件有望成为下一代NVM的最有力竞争者；而当前RRAM在高密度集成、低功耗及数据保持特性等一些方面仍有很多问题亟待解决。. 本课题围绕高集成、低功耗RRAM设计及纳米存储单元的实现开展研究，主要研究内容包括：CNT的生长与转移；过渡金属氧化物基存储材料工艺优化及存储器件构建；碳纳米管电极阻变器件的构建及性能测试；1S1R、互补结构RRAM的构建、电特性及其阻变机理研究。. 取得如下关键数据和结果：基于石英衬底的特殊处理，生长出水平定向的CNT，平均直径20nm左右；结合Au-热熔胶转移技术成功将石英衬底上的水平CNT转移至带有氧化层的Si衬底上。在生长氧化物阻变层基础上构建了CNT交叉电极阵列，在交叉点处构成了纳米RRAM单元器件。研究单层氧化物RRAM基础上，利用氧化钛-氧化铪掺杂和叠层技术改善器件功耗问题，有效降低reset电流至30nA，器件单元功耗小于1.0μW，获得了endurance>1E4器件窗口且无衰减，并探索出相关阻变机理为SCLC效应。此外，通过在Ta/TaOx/Pt器件中插入Ti金属层的方法实现了器件保持时间达1E5秒。基于氧化钒-氧化铪构建了1S1R及对称互补结构无源RRAM，完成低功耗高集成阵列RRAM的设计，为下一代新型非挥发存储器——无源高密度RRAM的研制提供相关理论和基础数据。