三维集成电路芯片导线互连与封装结构的精确电磁场分析

The technology of integrated circuit (IC) chips is a bottle neck in the development of our country's information industry and it has seriously affected our national safety and sustainable development of society and economics. The chip technology deals with many research areas. This project starts with the important stage of packaging and testing for chips and studies the accurate electromagnetic analysis method for interconnects and packaging structures of 3D chips by the approach of computer modeling and simulation. The study can generate novel algorithms and analysis software which can be used to extract parasitic circuit parameters of the packaging structures, which will be needed in the analysis of signal integrity and provide a strong support for optimally designing the packaging structures of 3D chips. Because of the complexity of 3D chips, currently there have not been accurate and effective electromagnetic analysis methods and software domestically and abroad. The existing analysis methods are mainly based on traditional 2D structures and they are not robust enough in function since many simplifications and approximations are adopted in model. These methods cannot satisfy the need of packaging for 3D chips. This project proposes a novel accurate electromagnetic analysis model and method based on the interconnecting and packaging structures of 3D chips and their characteristics include the consideration of loss and thickness of thin conducting interconnects, the use of novel volume-surface integral equations for modeling so as to overcome low-frequency breakdown and multiscale effect, and the employment of hybrid approach of combining the method of moments and Nyström scheme together in solutions, which incorporates the accelerator of fast multipole algorithm and novel treatment technique for singular integrals. The resulting algorithm and software will be validated to guarantee their effectiveness.

集成电路芯片技术是我国信息产业发展的瓶颈，严重影响国家安全与社会经济可持续发展。芯片技术涉及许多研究领域，本项目从芯片的封装与测试这一重要环节入手，通过计算机建模与仿真手段研究最新三维芯片的导线互连与封装结构的精确电磁场分析方法，形成新颖的算法与分析软件，用于提取作信号完整性分析所必须的电路寄生参数，为优化设计三维芯片的封装结构提供强有力的支持。由于三维芯片结构的复杂性，目前国内外尚缺少精确有效的电磁分析方法和软件，已有的分析方法主要基于传统的二维结构，功能不强且有较多的近似和简化，无法满足三维芯片的封装需求。本项目基于三维芯片的导线互连与封装结构，提出全新的精确电磁分析模型与方法，其特点包括考虑导体损耗与厚度、以新颖的体面积分方程建模克服低频崩溃和多尺度效应、求解时采用矩量法和Nyström方案相结合的混合方法并融入快速多极子算法加速器和新颖的奇异积分处理技术。相关算法和软件将通过验证确

三维（3D）集成电路芯片代表最新最前沿的芯片技术，严重制约我国的信息产业发展，急需掌握相关的核心技术。封装与测试是芯片技术中的重要一环，其优化设计强烈依赖于精确的电磁分析。本项目聚焦3D集成电路芯片中的导线互连与封装结构，提出新颖的电磁分析方法，通过计算机建模与仿真发展快速求解相关电磁控制方程的数值方法和算法，形成抽取电路寄生参数的可靠软件，用于封装结构中的信号完整性分析，为优化设计提供强有力的理论分析工具。项目研究内容主要包括建立新颖的电磁分析模型和提出新的数值求解方法两部分，通过四年的研究取得了如下的重要结果和关键数据：1）将结构中有损耗、薄厚度的导体看作可穿透介质体发展了两区域混合型面积分方程用于描述其电磁特性，使模拟更精确可靠；2）针对3D芯片中的复杂介质分布首次采用体积分方程描述并与导体部分的混合面积分方程耦合形成新型的体-面积分方程用于描述整个封装结构的电磁特性，大大提升了其对复杂结构的适应性；3）针对宽频带或全波分析需求，首次提出了扩展型体-面积分方程（AVSIEs）描述模型，用于抵抗低频和多尺度效应及低频崩溃；4）发展了将矩量法（MoM）与Nyström方案相结合的新型混合数值方法，用于精确求解上述体-面积分方程；5）基于上述体-面积分方程和MoM-Nyström混合数值方法发展了多层快速多极子算法（MLFMA）用于快速求解大型复杂问题；6）针对导体部分的高电导率积分核和介质部分的小长方体或小立方体网格分割发展了新颖的奇异性和超奇异性处理技术，用于精确计算相关的矩阵元素。上述重要结果均通过数值仿真验证了其有效性、适应性、精确性及与传统模型和求解方法相比的优越性，比如采用体积分方程描述介质部分可有效改善系统矩阵的性态、新颖奇异性处理方法可显著提高计算精度和效率。上述成果的科学意义在于发展了3D芯片封装结构中的电磁场理论、数学建模方法、数值算法技术，形成了相关的计算机仿真分析软件，为深刻理解和掌控其电磁特性提供了有效途径。