超高速多路时域交织SAR AD转换器开关时序及通道匹配技术研究

A/D converter is the interface between analog system and the digital system, for wireless communications, optical communications, and cognitive radar systems, A/D converter sampling rate gradually to GHz. Based on nano-scale CMOS technology, the project will mainly study the switch scheme, switch timing control circuit of ultrahigh speed time-interleaved SAR ADC, ultrahigh speed front-end sample-hold and timing technology, channel matching and calibration technology of multi-channel time-interleaved SAR ADC are also studied to achieve an ultrahigh speed 6-8 SAR ADC. By studying the charge redistribution technology, capacitive resolution techniques, high-speed, efficient and power saving switch scheme is achieved; based on the high-speed switching scheme, design the switch timing control circuit, analyzes the DLL and high-speed sample and hold structure, sampling clock is proposed, and can be combined with calibration techniques. By analyzing the mismatch between channels to achieve the calibration algorithm and the feasibility of the circuit structure for offset, gain, clock and bandwidth mismatch. Through the implementation of the project, to summarize the key design techniques for low power management, ultrahigh speed analog-digital conversion and multi-channel matching based on nanometer CMOS technology, and provide theoretical foundations for the application in next generation optical communications system and ultrahigh-speed equipment fields.

A/D转换器是模拟系统与数字系统的接口，对于无线通讯、光通信、认知雷达等系统，A/D转换器采样速率逐步向GHz发展。本项目基于纳米级CMOS工艺，深入研究超高速SAR A/D转换器开关时序、高速开关时序控制电路，突破超高速前端采样保持和时钟技术、多路时域交织SAR A/D转换器通道匹配及校准技术，实现6-8位超高速多路时域交织SAR A/D转换器。通过研究电荷重分配技术、电容拆分技术，实现高速、有效且节约功耗的开关时序及开关时序控制电路；分析DLL和高速采样保持器结构，提出针对超高速时域交织电路的合适采样时钟方案，并且可与校准技术融合；对通道间失配的研究分析，实现针对失调、增益、时钟、带宽失配的数字校准算法及可行性电路结构。通过项目的实施，探索并总结基于纳米级CMOS工艺的低功耗管理、超高速模数转换及多通道匹配的关键设计技术，为后续在下一代光传输系统和超高速仪器中应用奠定基础。

超高速模数转换器（A/D转换器）是无线通信、雷达对抗等电子信息系统的关键核心器件。本项目主要从超高速SAR A/D转换器开关时序，高速开关时序控制电路，超高速前端采样保持和时钟电路以及通道匹配误差分析和校准算法四个方面展开研究。在开关时序方面，提出了多种低功耗开关方式，其中所列举的三种开关时序相对于传统时序来说功耗在理论上分别降低了99.77%，99.37%和100%，面积上分别降低了大约97.65%，86%和50%。开关时序控制电路方面主要采用了异步逻辑提高了整体逻辑电路的速度，并使用2Bit/cycle的方法减少了比较周期，大大提高了SAR ADC的速度。时钟电路方面则采取了内嵌锁相环的方式获取纯净的时钟。高速前端采样保持应用衬底调制等技术消除了高频采样网络中的射频馈通效应，解决了高速ADC模拟采样带宽不足的问题。采用数字后台算法对时钟偏差、增益失配和失调失配分别进行校准。整体上设计了7位400MHz SAR ADC和10位600MHz SAR ADC等高速ADC芯片。本项目研究覆盖了理论建模，电路设计，版图绘制及流片测试，对超高速SAR ADC的研究具有良好的指导意义。