加速神经网络计算的可重构动态多核体系结构研究

Existing hardware platforms for neural network computing acceleration have many deficiencies. Through the introduction of reconfigurable computing and data-flow computing technology, this project starts the research on dynamic multi-core architecture to fully explore the specificities of neural network algorithms, such as intensive computation, complex communication, etc. Data-flow cache based reconfigurable instruction fetching and dispatching mechanism and data-flow block based instruction scheduling and execution mechanism can significantly improve the adaptability of multi-core processor on neural network algorithms to achieve scalable acceleration with high energy efficiency. The proposed microarchitecture can dynamically tune the width of pipeline stages such as fetch, issue, execute and memory access to meet the needs of specific algorithm; many physical cores can be fused together and function as a more powerful virtual core to adapt the complex operands communication. The project is based on the RISC-V open ISA. Firstly, we extend the ISA and build a simulator with function model, and the timing model will be added with the microarchitecture design process; Secondly, RTL code is developed and implemented on the FPGA platform to verify the validity of the research; At last, We study specific neural network application and research on crossing domains of brain-inspired computing and neuroscience.

本项目针对目前加速神经网络计算的各类型硬件的诸多不足，引入可重构计算与数据流计算技术，开展动态多核体系结构的研究，充分发掘神经网络算法计算密集、通信复杂等特点，设计多核处理器中基于数据流缓存的可重构指令获取与分发机制，以及基于数据流块的指令调度执行结构，显著提升多核处理器对神经网络算法的适应性，实现可扩展、高能效的加速计算。本项目提出的微结构能够根据神经网络算法的具体需求动态重构各物理核的取指、发射、执行、访存等流水线阶段的资源配置；同时为适应神经网络算法复杂的通信需求，多个物理核能够融合成更强的虚拟核提供计算能力。项目基于RISC-V开源指令集，首先进行指令集的扩展并搭建功能模拟器，并进行微结构设计完善模拟器的时序模型，然后进行RTL开发并在FPGA平台上实现，验证本项目研究成果的有效性，最后针对神经网络具体应用以及类脑计算、神经学等交叉学科开展研究。

本项目针对目前加速神经网络计算的各类型硬件的诸多不足，引入可重构计算与数据流计算技术，开展动态多核体系结构的研究，并以典型人工神经网络应用为例，进行分析研究。项目的成果主要有如下四项：第一、基于RISC-V开源指令集研发了低功耗、高能效、三级流水的处理器核，包括功能模拟器、时序模拟器、微架构设计与实现等工作。第二、研究动态多核技术，包括提升流水线前端指令供给能力的数据流缓存技术和使能多核融合的基于数据流块的指令调度技术，硬件实现在时序与面积方面仍存在问题。第三、以RISC-V处理器核为基础，以Xilinx的UltraScale zynq FPGA为载体，结合TVM开源神经网络编译器栈，搭建了全栈的神经网络加速应用研究平台。第四、针对稀疏神经网络加速和视频目标检测等问题进行研究。