面向高精度计算领域动态可配置加速器体系结构研究

With the development of semiconductor technology, the number of transistors on processor chip is increased and power consumption becomes the major bottleneck of chip performance. The way to customize accelerator for computing-intensive applications is used efficiently to ensure the chip performance trend with Moore’s law, improve the computational efficiency, and alleviate the problem of power consumption. However, beside of high performance, the demand for calculation accuracy is increased with the expansion of the scale in future scientific and engineering computing. It is required to provide effective hardware support for high-precision arithmetic.. In this project, we present an array accelerator architecture for high-precision application according to the development trend of processor and the demand of computation accuracy. Several schemes are proposed to balance performance, efficiency and scalability of this accelerator. First, a programmable unified hardware based-on VLIW structure is presented to implement varies of high-precision basic operations, elementary functions, and coarser-grain functions. Second, the accelerator architecture and memory structure are presented, which uses the latency tolerance scheme to accelerate the kernel programs featured with loop and uses the pipeline fold scheme to accelerate irregular kernel programs. Third, adaptive DMA engine architecture is presented to support multiple access modes to improve the utilization of data bandwidth. Final, reconfigurable array architecture is presented to implement data parallel with SPMD and functional pipeline with Systolic array. This project will provide several key techniques to increase the performance and accuracy for the next generation of supercomputers.

随着半导体技术的发展，芯片晶体管数量持续增加，功耗成为限制处理器性能提升的主要瓶颈。面向计算密集型应用领域定制加速器是保证芯片性能延续摩尔定律的发展趋势、提高芯片计算效率、缓解功耗问题的一种有效方法。然而，除了计算性能外，大规模科学和工程计算对处理器的计算精度也提出更高要求，迫切需要对高精度算术提供有效的硬件支持。. 课题结合处理器的发展趋势和计算精度需求，研究面向高精度计算阵列加速体系结构在性能、效率和扩展性方面所面临的挑战，研究基于VLIW可编程统一高精度基本功能计算引擎架构、支持延时容忍的可配置循环类加速策略和流水线折叠的可编程非规则类加速策略的计算加速核结构和存储架构、支持多种访存模式的自适应配置DMA数据引擎架构、支持SPMD数据并行模式和Systolic阵列功能流水并行模式的可配置多核阵列体系结构等关键技术，为下一代高效能计算机提供有力的计算能力和计算精度支持。

随着半导体技术的发展，功耗成为限制处理器性能提升的主要瓶颈。面向计算密集型应用领域定制加速器是提高芯片计算效率、缓解功耗问题的一种有效方法。同时，除了计算性能外，大规模科学和工程计算对处理器的计算精度也提出更高要求，迫切需要对高精度算术提供有效的硬件支持。. 课题结合处理器的发展趋势和计算精度需求，研究面向高精度计算阵列加速体系结构在性能、效率和扩展性方面所面临的挑战。研究了基于VLIW可编程统一高精度基本功能计算引擎架构，提出了统一低误差浮点TCORDIC算法，实现多种高精度基本函数和基本“宏”操作的计算；提出基于FIFO的延时容忍的可配置循环类加速策略和基于谓词执行的分支和循环优化策略的可编程非规则类加速策略；针对数据矩阵存储和矩阵行列交替访问进一步降低存储带宽利用率问题，提出基于基本块的矩阵转置算法，利用加速器内部存储器的实现DMA突发连续访问和基于“乒乓”方式的读写重叠策略，提高DDR存储带宽的利用率,获得73.6%的存储带宽利用率提升；基于上述策略，提出基于Systolic阵列功能流水并行模式的矩阵运算加速器和基于SPMD数据并行模式的可变精度FFT加速器，取得2个数量级的能效提升。. 本课题在加速器设计中的计算引擎、存储架构、访存模式和多核阵列中的并行模式等方面均取得了大量创新性研究成果，为面向领域的加速器设计与实现奠定坚实的理论和技术基础，具有重要的理论意义和应用价值。本课题全面完成了研究计划。