用于1S1R交叉阵列的选通器性能及模型研究

A crossbar array only consisting of RRAM cells suffers unavoidable cross-talk interference during the memory access operation due to sneak current among neighboring unselected cells. The 1S1R cell structure, in which the selector is conductive with good non-linearity performance, can effectively suppress the sneak current through the unselected memory cells of crossbar array. So the power consumption of crossbar array consisting of 1S1R cells can be reduced and the size of crossbar array can be increased. But at present, the structure and performance of Selector device are mainly studied on the basis of experiment, micro-structure characterizations and real-time monitoring, which requires advance experimental platform, expensive characterization and test instruments, and long experiment period. However, in this project, the structure of Selector will be designed and optimized by simulating its material and interface based on the first principle calculations. The mechanism of non-linearity conduction will be explored by simulating, theoretical analysis and curve fitting, and the compact model will be expected for Selector device. The 1S1R unit will be modeled for circuit simulating, and its SPICE model is to be tested and verified. The achievements of this project are expected to provide theoretical guidance and design ideas for large-scale integration and industrialization of 1S1R crossbar array.

RRAM存储单元构成的交叉阵列在存储器工作时，相邻单元之间的潜行电流会引起串扰现象。利用选通器的非线性传导特性构成的1S1R存储单元可以有效抑制交叉阵列的潜行电流，降低功耗，增加交叉阵列规模，从而提高集成度。目前对于选通器结构和器件性能主要是通过实验研制、显微表征和实时监测的方法进行研究，存在实验平台要求高、表征和测试仪器高端、实验周期长等问题。本项目拟基于第一性原理计算，对材料和界面进行多层次、多维度的模拟，探究选通器材料的改性和结构的优化；结合软件计算、理论分析和曲线拟合等研究手段，探索选通器非线性传导机制，建立Selector简约（compact）模型；为1S1R存储单元建立SPICE模型，在EDA软件中实现其存储功能并对其验证。该项目开展的研究内容及研究成果，将为实现1S1R交叉阵列较大规模集成及产业化提供理论指导和设计思路。

本项目研究了选通器（Selector）材料和结构，发现Ge2Sb2Te5、TiO2、SiO2等块状材料和h-BN、MoS2、α-GeTe、黑磷等新型二维材料具有较高的载流子迁移率、较好的热稳定性和机械柔性、优异的非线性，很有潜力作为Selector器件；基于这些材料，重点设计出了Ag/GR/Quartz/Pt、GR/ML α-GeTe/GR、Ti3C2/Black P/Ti3C2、GR/MoS·Si/GR等Selector器件，研究了其电流驱动能力、非线性比、阈值电压等主要特性，并利用掺入杂质、调节原子配比、改变界面接触、加入插层等方式进行材料改性或结构调整，进一步优化和完善器件性能。. 结合软件计算、理论分析和曲线拟合等手段，探究了选通器非线性传导机制。重点从界面肖特基势垒热发射、离子聚集与扩散效应、不同介质团簇间隧穿效应、窗函数的调节效应等角度，为忆阻器（包括Selector和RRAM器件）的输运机理建立了数学物理模型，然后结合实验测试结果，给出半经验电流电压计算公式，即compact模型。. 建立了一种直接用于电路仿真的1S1R Verilog模型，搭建了阵列电路，并为其设计了外围读、写和控制电路，通过优化Selector的性能参数（Vth, Vhold, RS-on, RS-off, NL）使到1S1R 交叉阵列读/写裕度和功耗等性能都有极大的改善。. 该项目的实施拓宽了Selector器件的应用领域，它不仅可以与RRAM器件构成1S1R存储单元，在EDA软件中实现其存储功能的仿真，为实现1S1R交叉阵列较大规模集成及产业化提供理论指导和设计思路。同时，Selector是一种易失性忆阻器，用于搭建神经元电路，实现神经网络算法硬件化，我们开展了其在强化学习、图像识别与分类等领域的延拓研究，有望将其应用于人工智能（AI）芯片或产品。