用于顶点探测器的高分辨、低功耗SOI像素芯片的若干关键问题的研究

Ultilizing a high performance SOI pixel detector process and combining with a novel in-pixel discrimination circuit, a method to shrink the pixel size with the function of in-pixel discrimination implemented in the mean time is to be studied, which aims at fulfiling the requirement of low power and hence solving the contradictive specifictions between space resolution and power consumption the vertex detector has to face in the high energy e+e- colliding experiment. This project will develope the key technology essential for domestic or international research on higgs physics and new physics. The research contents cover a few key issues tightly related to the design and optimization of pixel array, including pixel structure, signal/noise ratio, threshold dispersion, power consumption and layout. Some other aspects which are important but less related to the specific purpose of this project are excluded, such as zero suppresion and data transmission, radiation hardness, wafer thinning, beam test.

采用性能优良的SOI像素探测器工艺，结合新颖的像素内甄别电路，研究如何在缩小像素尺寸的同时实现像素内甄别功能，以满足低功耗的指标要求，从而解决高能e+e-对撞实验中顶点探测器所面临的空间分辨率与功耗之间的矛盾，为我国自主开展或者国际合作开展higgs物理研究以及新物理研究掌握关键的实验技术。研究内容紧紧围绕像素阵列的设计与优化相关的若干关键问题：包括像素结构、信噪比、阈值一致性、功耗以及版图等五个方面，其他一些重要但与研究目标不相关的问题不在研究范围之内，例如零压缩与数据传输，抗辐照性能，芯片减薄，束流实验等。

下一代高能e+e-对撞机利用质心系250GeV附近的e+e-对撞大量产生Higgs 粒子。Higgs衰变的次级顶点通过顶点探测器精确测量，从而给出其衰变分支比的测量结果。本项目采用性能优良的SOI像素探测器工艺，结合新颖的像素内甄别电路，通过模拟和实验两种手段验证了采用像素内甄别的小像素设计能够同时满足高分辨率和低功耗的要求，为高能e+e-对撞实验中顶点探测器的关键技术发展做出了有益探索。.像素芯片是建造顶点探测器的基本单元。本项目研制的SOI像素芯片验证了SOI工艺的全耗尽性能：即使在减薄为75um的情况下，仍然能够提供高达6000e-的电离信号，有效提高了信噪比；而基于200nm制程的前端电路设计将传统的列级甄别器向前移动到像素内，并且确保像素尺寸缩小到16um*16um。测试结果显示，利用相邻像素的电荷共享效应，空间分辨率最好可达到2.3um，满足高能e+e-对撞实验2.8um的空间分辨率要求；单个像素消耗的电流为1uA，相比传统的列级甄别读出降低了一个数量级。这项工作的创新性一方面体现在深刻理解并利用了SOI工艺的特点，推动了SOI工艺在顶点探测器中的应用；另一方面在于牢牢抓住空间分辨率这一核心目标并取得突破，这是下一代高能e+e-对撞实验的显著特征指标。相关结果发表在NIMA期刊(SCIE检索)，并受邀在国际学术会议Front-End Electronics 2018和International Workshop on High Energy Circular Electron Positron Collider报告。