静电感应晶体管栅源击穿电压的提高与关键工艺研究

Static Induction Transistors (SIT) have many advantages such as high operation frequency, high switching velocity, wide frequency band, low noise, large current capacity, high voltage gain, high output power and excellent radiation resistance. Although SIT has been researched for 30 years in our country, the studing progress is very slow, many key fabrication techniques not being solved. At present,the main difficulties for studing SIT are: (1) The electrical performances of SIT are sensitively dependent on geometric structure, material and technological parameters due to its narrow and short sizes of channel, resulting in the experimental results with large discrete distribution. (2) It is difficult to grow n type epitaxial layer with high resistivity on the p type gate region doped at high concentration because of self-doping effect. (3) The application region of SIT is mainly restricted by the low gate-source breakdown voltage. (4)In theory, the rectangular cylinder was simplicially used as structural model of gate region both by domestic or abroad scientists to analyze in analytical and numerical wany, the results given were not agree with the experiments. In this project, the elliptical cylinders will be used as the geometric structure model,that approaches practical structure of SIT further, to analyze the electrical potential and field distribution, the I-V characteristics, and breakdown mechanism between gate and source regions in depth both analytically and numerically. The key technologies and processes such as epitaxy, etching, diffusion and local oxidation for fabricating power static indution transistor will be experimentally researched and simulated, especially for growth of high resistive epitaxial film on highly doped gate region, to establish the optimum technologies and processes for manufacturing SIT with excellent performances.

静电感应晶体管(SIT)工作频率高，开关速度快，频带宽，电流容量大，电压增益高。目前SIT研究的难点在于：1)器件沟道尺寸又窄又短，其电学性能对几何尺寸、材料及工艺参数的变化敏感，实验结果离散性大；2）由于自掺杂效应，在高掺杂的p型栅体上方生长n型高阻外延层工艺难度大；3）栅源击穿电压低，应用范围受到限制；4)国内外采用过分简化的长方体栅体模型，作了比较粗糙的解析与数值分析，其结果和实验数据差距大。本项目将：1)建立符合SIT实际结构的椭圆柱状栅体模型，采用高斯定理、复合、散射与迁移率模型求解输运方程、连续性方程、泊松方程，对SIT的沟道电场、电势分布、I-V特性和击穿机理进行数值模拟和解析分析，求出SIT内部的各物理量；2)工艺模拟和实验研究，得到拟制自掺杂效应的工艺方法，改善外延层质量；3)合理的终端造型、表面造型、参数匹配调节和栅体掺杂优化等，提高栅源击穿电压,研制出高性能SIT。

静电感应晶体管(SIT)作为一种新型的半导体功率器件，工作频率高、开关速度快、频带宽、电流容量大、电压增益高。本项目对静电感应器件（SID）的新型结构、大电流特性、耐高压特性、动态特性和抗辐照特性方面进行了深入的研究。. 采用二维动态模型就静电感应晶闸管（SITH）开关性能对器件材料、几何结构尺寸和工艺参数的依赖关系进行了系统的研究，提出了一系列改善器件动态特性的工艺措施，并设计了多功能的开关参数测试电路，将SITH开关时间ton与toff降低到0.08μs与1.0μs，动态参数dv/dt超过1000V/S。从数值模拟和实验两方面研究了沟道载流子分布对SITH动态性能影响。推导了沟道少数载流子的数学表达式并分析了大注入下空间电荷分布对电流的控制机理。数值模拟与实验测试揭示了少子分布、沟道势垒与I-V特性及动态性能间的关系。建立了符合SIT实际结构的椭圆柱状栅体模型，采用高斯定理、复合、散射与迁移率模型求解输运方程、连续性方程、泊松方程，对SIT的沟道电场、电势分布、I-V特性和击穿机理进行数值模拟和解析分析，求出了SIT内部的各物理量。提出了一种新型横向结构的静电感应晶体管（TSIT），并对其基本的电特性及频率特性进行了深入研究。研究结果表明：相对传统的垂直沟道SIT而言，TSIT器件利用简单的结构及工艺不仅获得了较高的栅-源击穿电压及较好的电流-电压特性，同时获得了超过100MHz工作频率。深入研究了辐射导致SIT性能退化的物理机理，从理论和实验两方面对SIT的抗辐射特性进行深入研究，以得涵盖辐照剂量、辐照能量、工艺参数、器件结构、材料等参数的I-V特性解析表达式。. 本项目研究成果发展和进一步完善了静电感应器件的理论，从器件结构及工艺方面提高了SID的大电流、大电压、抗辐照等性能。在避免器件结构设计的盲目性，深入认识材料、几何结构、工艺参数和电性能之间的制约关系有着重要的促进作用，也为推进SID理论的发展及高性能SID研制提供了理论和实验依据。