高Ge组分SGOI衬底上Hf基高k介质材料的研究

When the integrated circuit (IC) feature size is scaling down to deep nanometers, the physical limit of traditional silicon process is being approached and several problems emerged: short-channel effect, drift of threshold voltage and increase of current leakage, which have became a bottle neck of IC development. Such new techniques as high mobility channel material and novel gate dielectric are the key of dealing with the problems. In this project, aiming to the applications of Hf-based high-k material on SGOI with a high carrier mobility, performance and related mechanism of the material system will be studied exhaustively. High Ge content SGOI substrate will be fabricated through modified Ge condensation and multi-step condensation，then a condensation module will be built. For studying of HfO2/SiO2 stacking material, a key technique using the condensation mechanism and a special thinning method is proposed to prepare ultrathin SiO2 layer on SGOI. By means of systematic experiments, revealing the mutual influence among the materail thickness, component, structure, interface and electrical properties，and invealing the effect mechanism of Ge content to high k dielectric layers. On the basis of above study, this project will develop a solution of high k material on SGOI with a high Ge content, which can supply thinner equivalent oxide thickness(EOT) and lower leakage current density. Therefore, the study will help drive the application of Hf-based high k dielectric on SGOI substrate that can offer a high carrier mobility.

随着尺寸等比例缩小逐渐逼近体硅技术的物理极限，短沟道效应、阈值电压漂移、漏电流增大等问题成为制约集成电路发展的瓶颈，而高迁移率沟道材料和新型栅介质等新技术是解决问题的关键。本项目以Hf基高k材料在高迁移率衬底材料SGOI上的应用为目的，对其性能和相关机理展开研究。利用改良型Ge浓缩和分步浓缩法制备高Ge组分SGOI衬底材料，研究其浓缩机理，建立相应的浓缩模型；为研究HfO2/SiO2堆垛高k层性能，借助提出的浓缩机理和特殊减薄法解决在SGOI上制备超薄SiO2层的关键技术问题；通过系统实验和理论分析，研究材料厚度、组分、结构、界面和电学性能等因素之间的相互影响，揭示衬底Ge组分对高k介质层性能的影响机理。以此为依据，开发在高Ge组分SGOI上等效栅氧厚度较小和漏电流密度较低的高k材料，推动Hf基高k介质在高迁移率衬底SGOI上的应用。

本项目采用改进Ge浓缩工艺，通过系统性实验构建了Ge组分（10.4%-97.8%）可控的SGOI制备方法。考虑到堆垛高k介质层的优势，探索出对SGOI样品进行快速处理的化学氧化法，在SiGe表面获得1.1nm超薄SiO2氧化层并在制备了HfO2/SiO2堆垛介质层。在SGOI上制备了不同厚度的HfO2薄膜，获得最小等效栅氧厚度为1nm。主要利用C-V曲线分析了SGOI上Hf基高k介质电学性能受到衬底Ge组分变化的影响规律：当HfO2厚度在5nm左右且含有中间超薄SiO2缓冲层时，介质层以及整个样品结构的电学特性受到衬底Ge组分影响较为明显（Ge组分低于46%），而在Ge组分处于46%到78.8%之间时，电学性能趋于稳定；当HfO2厚度达到20nm时，样品组无论在电容值上还是在C-V曲线走势上，其稳定性都大为提升，其电容值呈现了先增大再减小的趋势，转折点为Ge组分=46%的样品；当HfO2介质厚度达到30nm时，一方面用磁控溅射法沉积HfO2的厚度已经趋于饱和难以再大幅增加，另一方面此时的样品组在电容值和C-V曲线走势上也呈现了高度稳定的特性，即几乎不受衬底Ge组分的影响。利用有限元法建立了基于SiGe和高k介质的纳米尺寸MOS场效应管，数值模拟表明，当前在体Si器件上使用较普遍的高性能Hf基高k材料，选取合适的厚度，用在对应纳米尺寸的Si1-xGex(x>60%)衬底CMOS场效应管器件上，一方面可以避免纯 Ge器件在工艺实现的难题，另一方面可以大大提升CMOS器件的性能。此外，在SGOI样品上成功外延了应变量为1%的全局应变硅薄膜，并研究了应变硅薄膜在纳米尺寸下的应变弛豫情况，结果表明当应变硅尺度小于200nm时会发生应变弛豫，但由于衬底SiGe的牵制作用，而使应变硅的应变弛豫度并不大。自立项以来，项目组成员共发表论文11篇，其中EI/SCI收录8篇，完成了预期目标，培养本科生3名，且均已考取研究生。